Xilinx Virtex-II Pro PPC405, Руководство пользователя

Страница: 139 / 562

March 2002 Release www.xilinx.com 447
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Accessing Memory
R
Data-Cache Hint Instructions
The PowerPC architecture defines data-cache instructions that can be used to improve
memory performance by providing hints to the processor that memory locations are likely
to be accessed in the near future. They are:
• Data-cache block touch ( dcbt )—This instruction indicates that memory loads are likely
to occur from the specified address. The processor can prefetch the cacheline
associated with the address as a result of executing this instruction.
• Data-cache block touch for store ( dcbtst )—This instruction indicates that memory stores
are likely to occur to the specified address. The processor can prefetch the cacheline
associated with the address as a result of executing this instruction.
Depending on how a processor implementation interacts with the memory subsystem,
dcbt and dcbst can behave differently. On the PPC405, however, dcbt and dcbtst are
implemented identically. These instructions execute as a no-operation if loading the
cacheline were to result in a page-translation exception or a protection exception.
The following instructions can also be used as hint instructions when the contents of an
address in system memory are not important:
• Data-cache block allocate (
dcba
)—This instruction allocates a cacheline corresponding to
the specified address.
• Data-cache block zero ( dcbz )—This instruction allocates a cacheline corresponding to
the specified address and clears the cacheline contents to zero. It can be used to
initialize cacheable memory locations.
dcba and dcbz do not access memory when allocating a cacheline. It is possible for these
instructions to allocate cachelines for non-existent physical-memory addresses. A
subsequent attempt to store the cacheline contents back to system memory can result in
system problems or cause a machine-check exception to occur.
The dcba instruction executes as a no-operation if loading the cacheline were to result in a
page-translation exception or a protection exception. On the other hand, dcbz causes a
data-storage interrupt to occur if loading the cacheline results in a page-translation
exception or a protection exception.
Accessing Memory
Memory (collectively, system memory and cache memory) is accessed when instructions
are fetched and when a program executes load and store instructions. Other conditions not
specified by a program can cause memory accesses to occur, such as cacheline fills and
Table 5-1: Data-Cache to PLB Priority Examples
If the Current DCU
Operation...
...Has the
Following
DPP
0
Value...
The Next DCU Operation...
...Updates DPP
0
as Shown
Load from system memory. Assert See first column
Store to system memory
Deassert
Any stalled DCU operation Assert
dcbf Cache hit Deassert
dcbf, dcbst Non-cacheable load Assert
dcbf, dcbst Cacheline flush Assert
dcbt Cache hit Deassert
dcbi, dccci, dcbz Deassert See first column