Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 479
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Translation Look-Aside Buffer
R
TLB Access
When the MMU translates a virtual address (the combination of PID and effective address)
into a physical address, it first examines the appropriate shadow TLB for the page-
translation entry. If an entry is found, it is used to access physical memory. If an entry is not
found, the MMU examines the UTLB for the entry. A delay occurs each time the UTLB
must be accessed due to a shadow TLB miss. For the ITLB, the miss latency is four cycles.
The DTLB has a miss latency of three cycles. The DTLB has priority over the ITLB if both
simultaneously access the UTLB.
Figure 6-7 shows the logical process the MMU follows when examining a page-translation
entry in one of the shadow TLBs or the UTLB. All valid entries in the TLB are checked. In
the PPC405, all entries in a specific TLB (shadow or unified) are examined simultaneously.
A
TLB hit occurs when all of the following conditions are met by a TLB entry:
• The entry is valid.
• The TAG field in the entry matches the EA[EPN] under the control of the SIZE field in
the entry.
• The TID field in the entry matches the PID.
If any of the above conditions are not met, a TLB miss occurs. A TLB miss causes an
exception, as described in TLB-Access Failures , page 480 .
A TID value of 0x00 causes the MMU to ignore the comparison between the TID and PID.
Only the TAG and EA[EPN] are compared. A TLB entry with TID
=
0x00 represents a
process-independent translation. Pages that are accessed globally by all processes should
be assigned a TID value of 0x00.
A PID value of 0x00 does not identify a process that can access any page. When PID
=
0x00,
a page-translation hit only occurs when TID
=
0x00.
It is possible for software to load the TLB with multiple entries that match an EA[EPN] and
PID combination. However, this is considered a programming error and results in
undefined behavior.
When a hit occurs, the MMU reads the RPN field from the corresponding TLB entry. Some
or all of the bits in this field are used, depending on the value of the SIZE field (see
Table 6-2, page 478 ). For example, if the SIZE field specifies a 256 KB page size, RPN
0:13
represents the physical page number and is used to form the physical address. RPN
14:21
is
not used, and software must clear those bits to 0 when initializing the TLB entry. The
remainder of the physical address is taken from the page-offset portion of the EA. If the
page size is 256 KB, the 32-bit physical address is formed by concatenating RPN
0:13
with
EA
14:31
.
Prior to accessing physical memory, the MMU examines the TLB-entry access-control
fields. These fields indicate whether the currently executing program is allowed to
perform the requested memory access. See
Virtual-Mode Access Protection , page 482 , for
more information.
If access is allowed, the MMU checks the storage-attribute fields to determine how to
access the page. The storage-attribute fields specify the caching policy and byte ordering
for memory accesses. See
Storage-Attribute Fields , page 478 , for more information.
1 MB 0b101 TAG
0:11
↔
EA
0:11
EA
12:31
RPN
0:11
12:21 12
4 MB 0b110 TAG
0:9
↔
EA
0:9
EA
10:31
RPN
0:9
10:21 10
16 MB 0b111 TAG
0:7
↔
EA
0:7
EA
8:31
RPN
0:7
8:21 8
Table 6-2: Page-Translation Bit Ranges by Page Size
Page
Size
SIZE
(TLB Field)
Tag Comparison
Bit Range
Page
Offset
Physical-Page
Number
RPN Bits
Clear to 0
n
( Figure 6-1 )