Xilinx Virtex-II Pro PPC405, Руководство пользователя

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356 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 2: Operational Concepts
R
• Load string instructions
• Integer compare instructions
On the PPC405, attempting to execute an invalid instruction form generally yields a
boundedly-undefined result, although in some cases a program exception (illegal-
instruction error) can occur.
Optional Instructions
The PowerPC architecture allows implementations to optionally support some defined
instructions. The PPC405 does not implement the following instructions:
• Floating-point instructions
• External-control instructions ( eciwx , ecowx )
• Invalidate TLB entry ( tlbie )
Illegal Instruction Class
Illegal instructions are grouped into the following categories:
• Unused primary opcodes. The following primary opcodes are defined as illegal but
can be defined by future extensions to the architecture:
1, 5, 6, 56, 57, 60, 61
• Unused extended opcodes. Unused extended opcodes can be derived from
information in
Instructions Sorted by Opcode , page 781 . The following primary
opcodes have unused extended opcodes:
19, 31, 59, 63
• An instruction consisting entirely of zeros is guaranteed to be an illegal instruction.
This increases the probability that an attempt to execute data or uninitialized memory
causes an illegal-instruction error. If only the primary opcode consists of all zeros, the
instruction is considered a reserved instruction, as described in the following section.
An attempt to execute an illegal instruction causes an illegal-instruction error (program
exception). With the exception of an instruction consisting entirely of zeros, illegal
instructions are available for future addition to the PowerPC architecture.
Reserved Instruction Class
Reserved instructions are allocated to specific implementation-dependent purposes not
defined by the PowerPC architecture. An attempt to execute an unimplemented reserved
instruction causes an illegal-instruction error (program exception). The following types of
instructions are included in this class:
• Instructions for the POWER architecture that have not been included in the PowerPC
architecture.
• Implementation-specific instructions used to conform to the PowerPC architecture
specification. For example,
load data-TLB entry ( tlbld ) and load instruction-TLB entry
( tlbli ) instructions in the PowerPC 603™.
• The instruction with primary opcode 0, when the instruction does not consist entirely
of binary zeros.
• Any other implementation-specific instruction not defined by the PowerPC
architecture.
PowerPC Embedded-Environment Instructions
To support functions required in embedded-system applications, the PowerPC embedded-
environment architecture defines instructions that are not part of the PowerPC
architecture.
Table 2-4 lists the instructions specific to the PPC405 and other PowerPC
embedded-environment family implementations. From the standpoint of the PowerPC
architecture, these instructions are part of the reserved class and are implementation