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March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Appendix D:
Programming Considerations
R
shows an example of a 5-word unaligned operand. Shaded boxes represent
bytes outside the operand that are discarded by the processor.
In the above example, access to the multiple-word operand requires six cycles, assuming
data-cache hits. This is calculated as follows:
•
One cycle is required to access the first three bytes of word 0. The byte at address 0 is
also accessed but discarded.
•
Four cycles are required to access the remaining byte of word 0, all bytes in words 1, 2,
and 3, and the first three bytes of word 4.
•
One cycle is required to access the last byte in word 4. The bytes at addresses 21, 22,
and 23 are also accessed but discarded.
Instruction Cache Misses
Cacheable instruction-fetch misses and non-cacheable instruction-fetches incur penalty
cycles for accessing memory over the PLB. These penalty cycles depend on the speed of the
PLB and when the address acknowledge is returned over the PLB. The number of penalty
cycles are as follows:
•
Three cycles if the access is a sequential instruction fetch.
•
Four cycles if the access is due to a taken branch recognized by the instruction
prefetch buffer.
•
Five cycles if the access is due to a taken branch recognized by the instruction decode
unit.
The above penalty cycle numbers assume the following:
•
The PLB operates at the same frequency as the processor.
•
The address acknowledge is returned in the same cycle the data-cache unit asserts the
PLB request.
•
The target instruction is returned in the cycle following the address acknowledge.
Additional cycles are required if the system performance does not match the above
assumptions.
Address
0
4
8
12
16
20
Data
0
1
2
3
4
Figure D-2:
Multiple-Word Access Example
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