Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 339
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
PPC405 Features
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Device Control Register
The device control register (DCR) bus interface supports the attachment of on-chip registers
for device control. Software can access these registers using the mfdcr and mtdcr
instructions.
Clock and Power Management
The clock and power-management interface supports several methods of clock distribution
and power management.
JTAG Port
The JTAG port interface supports the attachment of external debug tools. Using the JTAG
test-access port, a debug tool can single-step the processor and examine internal-processor
state to facilitate software debugging. This capability complies with the IEEE 1149.1
specification for vendor-specific extensions, and is therefore compatible with standard
JTAG hardware for boundary-scan system testing.
On-Chip Interrupt Controller
The on-chip interrupt controller interface is an external interrupt controller that combines
asynchronous interrupt inputs from on-chip and off-chip sources and presents them to the
core using a pair of interrupt signals (critical and noncritical). Asynchronous interrupt
sources can include external signals, the JTAG and debug units, and any other on-chip
peripherals.
On-Chip Memory Controller
An on-chip memory (OCM) interface supports the attachment of additional memory to the
instruction and data caches that can be accessed at performance levels matching the cache
arrays.