Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 511
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Interrupt Reference
R
Program Interrupt (0x0700)
Interrupt Classification
• Noncritical—return using the rfi instruction.
• Synchronous.
• Precise.
Description
Program exceptions are caused by any of the following conditions:
• Attempted execution of an illegal instruction. Floating-point instructions are
considered illegal instructions in the PPC405D5.
• Attempted execution of a privileged instruction from user mode.
• Execution of a trap instruction that satisfies the trap conditions. Following execution
of a trap instruction, SRR0 contains the address of the trap instruction. To avoid
repeated program interrupts as a result of returning from the trap handler, software
should either:
-
Replace the trap instruction with a non-trapping instruction.
- Modify the trap conditions to prevent a program interrupt.
- Modify the address in SRR0 to point to the next-sequential instruction in the
interrupted program prior to executing the
rfi .
The following exception conditions do not occur on the PPC405D5 but can occur on other
versions of the PowerPC 405 processor:
• Exceptions caused by attempting to execute an unimplemented FPU or APU
instruction. This exception condition sets ESR[PEU]
=
1.
• Exceptions caused by FPU-instruction errors. This exception condition sets
ESR[PFP]
=
1.
• Exceptions caused by APU-instruction errors. This exception condition sets
ESR[PAP]
=
1.
Software cannot disable program interrupts.
Affected Registers
Register Value After Interrupt
SRR0 Loaded with the effective address of the instruction that caused the program
exception.
SRR1 Loaded with a copy of the MSR at the point the interrupt occurs.
SRR2 Not used.
SRR3