354
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 2:
Operational Concepts
R
Alignment Exceptions
Misalignment occurs when addresses are not evenly divided by the data-object size. The
PPC405 automatically handles misalignments within word boundaries and across word
boundaries, generally at a cost in performance. Some instructions cause an alignment
exception if their operand is not properly aligned, as shown in
Cache-control instructions ignore the four least-significant bits of the EA. No alignment
restrictions are placed on an EA when executing a cache-control instruction. However,
certain storage-control attributes can cause an alignment exception to occur when a cache-
control instruction is executed. If data-address translation is disabled (MSR[DR]=0) and a
dcbz
instruction references a non-cacheable memory region, or the memory region uses a
write-through caching policy, an alignment exception occurs. The alignment exception
allows the operating system to emulate the write-through caching policy. See
for more information.
Instruction Conventions
Instruction Forms
Opcode tables and instruction listings often contain information regarding the instruction
form
. This information refers to the type of format used to encode the instruction. Grouping
instructions by format is useful for programmers that must deal directly with machine-
level code, particularly programmers that write assemblers and disassemblers.
The formats used for the instructions of the PowerPC embedded-environment architecture
are shown in
. The
also shows the form used by each instruction, listed alphabetically by mnemonic.
Table 2-2:
Performance Effects of Operand Alignment
Operand
Boundary Crossing
Size
Byte Alignment
None
Cache Block
Page
Byte
1
Optimal
Not Applicable
Halfword
2
Optimal
Not Applicable
1
Good
Good
Poor
Word
4
Optimal
Not Applicable
<4
Good
Good
Poor
Multiple Word
4
Good
Good
Good
1
Byte String
1
Good
Good
Poor
Note:
Assumes both pages have identical storage-control attributes. Performance is poor
otherwise.
Table 2-3:
Instructions Causing Alignment Exceptions
Mnemonic
Condition
dcbz
EA is in non-cacheable or write-through memory.
dcread, lwarx, stwcx
EA is not word aligned.
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