Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 441
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Memory-System Organization
R
When a hit occurs, the cacheline with the matching tag is selected. The data in the selected
cacheline is loaded into the 32-byte data-cacheline buffer. The byte field in the data address
is used as an offset into the line buffer. The data located at that byte offset (byte, halfword,
or word) is read from or written to the line buffer, depending on the operation that initiated
the cache access.
Access into the instruction cache operates in a near-identical fashion. The difference is in
how the 32-byte instruction line buffer is accessed. The line buffer is accessed using the
byte field from the instruction effective address. However, the low-order two bits (EA
30:31
)
are ignored, aligning the access on a word boundary. Four bytes are always read from this
word-aligned location in the instruction cacheline buffer.
Instruction-Cache Operation
Figure 5-5 shows how instructions flow from the instruction-cache unit (ICU) to the
execution pipeline.
All instruction-fetch requests are handled by the ICU. If a fetch address is cacheable, the
ICU examines the instruction cache for a hit. When a hit occurs, the cacheline is read from
the instruction cache and loaded into the line buffer. Individual instructions are sent from
the line buffer to the instruction queue. From there they are either loaded into one of the
prefetch buffers or are immediately decoded, depending on the current state of the decode
and execution pipelines. Up to two instructions per clock cycle can be sent to the
instruction queue from the line buffer.
When a cache miss occurs, or when an instruction address is not cacheable, the ICU sends
the fetch-address request to system memory over the processor local bus (PLB). A cache
miss results in a cacheline fill, which appears as an eight-word request on the PLB. The
request size for non-cacheable instructions can be either four words (half line) or eight
words (full line) and is programmable using the CCR0 register (see
Core-Configuration
Register , page 459 ). Full-line (cacheable and non-cacheable) and half-line fetch requests
are always completed (never aborted), even if the instruction stream branches before the
Figure 5-5: Instruction Flow from the Instruction-Cache Unit
Fill Buffer
UG011_43_033101
Processor Local Bus
I-Cache
Array
I-Cache
Tags
Prefetch Buffer 0
Prefetch Buffer 1
Decode
Execute
Instructions
Bypass
Fetch-Request
Address
Fetch Address
ICU
Line Buffer