Xilinx Virtex-II Pro PPC405, Руководство пользователя

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480 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 6: Virtual-Memory Management
R
TLB-Access Failures
A TLB-access failure causes an exception to occur. This interrupts execution of the
instruction that caused the failure and transfers control to an interrupt handler to resolve
the failure. A TLB access can fail for two reasons:
• A matching TLB entry was not found, resulting in a TLB miss.
• A matching TLB entry was found, but access to the page was prevented by either the
storage attributes or zone protection.
When an interrupt occurs, the processor enters real mode by clearing MSR[IR, DR] to 0. In
real mode, all address translation and memory-protection checks performed by the MMU
are disabled. After system software initializes the UTLB with page-translation entries,
management of the PPC405 UTLB is usually performed using interrupt handlers running
in real mode.
Figure 6-7: General Process for Examining a TLB Entry
UG011_41_033101
Check Access
Read TLBLO[RPN]
using TLBHI[SIZE]
TLBHI[V]=1
TLBHI[TID]=0x00
Compare
TLBHI[TID] with PID
Compare
TLBHI[TAG] with EA[EPN]
using TLBHI[SIZE]
Yes
No Yes
Match
Match (TLB Hit)
Check for
Guarded Storage
Instruction Fetch Data Reference
Allowed
Not Guarded
Extract Offset from EA
using TLBHI[SIZE]
Generate Physical Address
from TLBLO[RPN] and Offset
TLB-Entry Miss
No Match
Storage Violation
Guarded
Access Violation
Not Allowed
No
TLB-Entry Miss
TLB-Entry Miss
No Match
Check TLB-Entry
Using Virtual Address