March 2002 Release
559
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
R
BSDL
The
boundary-scan description language
(BSDL) provides a description of
component testability features. It is used by automated test-pattern generation
tools for package-interconnect tests and by electronic design-automation
(EDA) tools for verification and for synthesizing test logic. BSDL supports
extensions that can be used for internal-test generation and to write software
for hardware debugging and diagnostics.
The primary components of BSDL include:
•
The
logical-port description
, which assigns symbolic names to each pin at
the chip level. Pins are also assigned a logical-type description of
in
,
out
,
inout
,
buffer
, or
linkage
. This description defines the direction of
information flow through the pin.
•
The
physical-pin map
, which provides correlation between the chip-level
logical ports and the physical pin locations on a specific package. A BSDL
description can contain several physical pin maps that describe different
packages. Every pin map within the BSDL description is given a unique
name.
•
The
instruction statements
, which describe bit patterns that must be shifted
into the instruction register to place the chip into the various test modes
defined by the BSDL standard. Instruction-statements also support
instruction descriptions unique to the chip.
•
The
boundary-register description
, which lists each shift cell (also known as
a shift stage) in the boundary register. Each cell is numbered. Cell 0 is
defined as the cell closest to the test-data out (TDO) pin. The cell with the
highest number is defined as the cell closest to the test-data in (TDI) pin.
Cells contain additional information, including the cell type, the logical
port associated with the cell, the logical function of the cell, the “safe”
value for the cell, the “disable” value for the cell, the reset value for the
cell, and a control number.
For more information, refer to IEEE standard 1149.1b-1994, which defines
BSDL. This standard is a supplement to IEEE standards 1149.1-1990 (standard
test-access port) and 1149.1a-1993 (boundary-scan architecture). BSDL is a
subset of the
VHSIC hardware description language
(VHDL), a standard defined
by IEEE 1076-1993.
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