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March 2002 Release
837
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
R
Appendix D
Programming Considerations
This appendix provides programming examples that can be useful in embedded
applications.
Synchronization Examples
The following provides general guidelines for using the
lwarx
and
stwcx.
instructions:
•
The
lwarx
and
stwcx.
instructions should be paired and use the same effective
address (EA).
•
An unpaired
stwcx.
instruction to an arbitrary EA (scratch address) can be used to
clear any reservation held by the processor.
•
An
lwarx
instruction can be left unpaired when executing certain synchronization
primitives if the value loaded by the
lwarx
is not zero.
provides
such an example.
•
Minimizing the looping on an
lwarx
/
stwcx.
pair increases the likelihood that forward
progress is made. The sequence shown in
provides such an
example. This example tests the old value before attempting the store. If the order is
reversed (store before load), more
stwcx.
instructions are executed and reservations
are more likely to be lost between the
lwarx
and the
stwcx.
instructions.
•
Performance can be improved by minimizing looping on an
lwarx
instruction that
fails to return a desired value. Performance can also be improved by using an
ordinary load instruction to do the initial value check, as follows:
loop:
lwz
r
5,0(
r
3) #load the word
cmpwi
r
5,0
#compare word to 0
bne-
loop
#loop back if word not equal to 0
lwarx
r
5,0,
r
3
#try reserving again
cmpwi
r
5,0
#compare likely to succeed
bne
loop
stwcx. r
4,0,
r
3
#try to store nonzero
bne-
loop
#loop if reservation lost
•
Livelock is a state where no progress is made in a multiprocessor environment due to
the interaction of the processors. Livelock is possible if a loop containing an
lwarx
/
stwcx.
pair also contains an ordinary store instruction that affects one or more
bytes in the reservation granule. For example, the first code sequence shown in
can cause livelock if two list elements have next element pointers
in the same reservation granule.
The examples in this appendix show how synchronization instructions are used to emulate
various synchronization primitives and how more complex forms of synchronization can
be implemented. Each example assumes that a similar instruction sequence is used by all
processes requiring synchronization of the accessed data. The examples show a
conditional sequence that begins with an
lwarx
instruction. This can be followed by
memory accesses and/or computations on the loaded value. The sequence ends with a
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