838
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Appendix D:
Programming Considerations
R
stwcx.
instruction
.
In most of the examples, failure of the
stwcx.
instruction causes a branch
back to the
lwarx
for a repeated attempt. The examples are optimized for the case where
the
stwcx.
instruction succeeds by having the conditional-branch prediction bit set
appropriately.
Fetch and No-Op
The
fetch and no-op
primitive atomically loads the current value in a memory word. This
example assumes that the address of the memory word is in
r
3 and the data is loaded into
r
4.
loop:
lwarx
r
4,0,
r
3
#load and reserve
stwcx
.
r
4,0,
r
3
#store old value if still reserved
bne-
loop
#loop if reservation lost
If the
stwcx.
succeeds, the destination location is updated with the same value that was
loaded by the preceding
lwarx
. Although this store is unnecessary with respect to the
value in the memory location, its success ensures that the value loaded by the
lwarx
was
the most current value.
Fetch and Store
The
fetch and store
primitive atomically loads and replaces a memory word. This example
assumes that the address of the memory word is in
r
3, the new data is stored from
r
4, and
the old data is loaded into
r
5.
loop:
lwarx
r
5,0,
r
3
#load and reserve
stwcx
.
r
4,0,
r
3
#store new value if still reserved
bne-
loop
#loop if reservation lost
Fetch and Add
The
fetch and add
primitive atomically increments a memory word. This example assumes
that the incremented (new) data is stored from
r
0, the address of the memory word to be
incremented is in
r
3, the increment value is contained in
r
4, and the data to be incremented
is loaded into
r
5.
loop:
lwarx
r
5,0,
r
3
#load and reserve
add
r
0,
r
4,
r
5 #increment word
stwcx
.
r
0,0,
r
3
#store new value if still reserved
bne-
loop
#loop if reservation lost
Fetch and AND
The
fetch and AND
primitive atomically ANDs a value into a memory word. This example
assumes that the ANDed (new) data is stored from
r
0, the address of the memory word to
be ANDed is in
r
3, the AND value is contained in
r
4, and the data to be ANDed is loaded
into
r
5.
loop:
lwarx
r
5,0,
r
3
#load and reserve
and
r
0,
r
4,
r
5 #AND word
stwcx. r
0,0,
r
3
#store new value if still reserved
bne-
loop
#loop if reservation lost
The above sequence can be changed to perform any atomic boolean operation on a
memory word.
Test and Set
This version of the
test and set
primitive atomically loads a word from memory, ensures
that the memory word is a nonzero value, and updates CR0[EQ] according to whether the
value loaded is zero. This example assumes that the address of the memory word is in
r
3,
the new (nonzero) data is stored from
r
4, and the old data is loaded into
r
5.
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