Xilinx Virtex-II Pro PPC405, Руководство пользователя

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490 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 7: Exceptions and Interrupts
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Certain interrupts can be disabled (masked) or enabled (unmasked). Disabling an
interrupt prevents it from occurring when the corresponding exception condition is
detected by the processor.
Synchronous and Asynchronous Exceptions
Exceptions (and the corresponding interrupt) can be synchronous or asynchronous.
Synchronous exceptions are directly caused by the execution or attempted execution of an
instruction. Asynchronous exceptions occur independently of instruction execution. The
cause of an asynchronous exception is generally not related to the instruction executing at
the time the exception occurs.
Precise and Imprecise Interrupts
Most interrupts are precise. A precise interrupt occurs in program order and on the
instruction boundary where the exception is recognized. A precise interrupt causes the
following to occur:
• The return address points to the excepting instruction. For synchronous exceptions,
the return address points to either the instruction causing the exception or the
instruction that immediately follows, depending on the exception condition. For
asynchronous exceptions, the return address points to the instruction boundary
where the exception is recognized by the processor.
• All instructions preceding the excepting instruction complete execution before the
interrupt occurs. However, it is possible that some storage accesses initiated by those
instructions are not complete with respect to external devices.
• Depending on the exception condition, it is possible for the excepting instruction to
have completed execution, partially completed execution, or not have begun
execution.
• No instructions following the excepting instruction are executed prior to transferring
control to the interrupt handler.
When a imprecise interrupt occurs, the excepting instruction is unrelated to the exception
condition. Here, there is a delay between the point where the exception is recognized by
the processor and the time when the interrupt occurs. An imprecise interrupt causes the
following to occur:
• The excepting instruction follows (in program order) the instruction boundary where
the exception is recognized by the processor. The delay can span several instructions.
• All instructions preceding the excepting instruction complete execution before the
interrupt occurs. However, it is possible that some storage accesses initiated by those
instructions are not complete with respect to external devices.
• It is possible for the excepting instruction to have completed execution, partially
completed execution, or not have begun execution.
• No instructions following the excepting instruction are executed prior to transferring
control to the interrupt handler.
On the PPC405, only the machine-check interrupt is imprecise. A machine check can be
caused indirectly by the execution of an instruction. In this case, it is possible for the
processor to execute additional instructions before recognizing the occurrence of a
machine check.
Partially-Executed Instructions
Certain instructions can cause an alignment exception or data-storage exception part-way
through their execution. When an interrupt occurs, some software-visible state can be
updated to reflect the partial execution of the excepting instruction. The instructions and
the effect interrupts have on partial execution are as follows:
• Load-multiple and load-string instructions.