March 2002 Release
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Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Memory-System Control
R
Memory-System Control
Software manages memory-system operation using a combination of synchronization
instructions (described in the previous section) and storage attributes. These resources
provide program control over memory coherency, memory-access ordering, and
speculative memory accesses
Storage Attributes
Storage attributes are used by system software to control how the processor accesses
memory. These attributes are used to control cacheability, endianness (byte-ordering), and
speculative accesses. PPC405 software can control five different storage attributes. Three
attributes—write through (W), caching inhibited (I), and guarded (G)—are defined by the
PowerPC architecture. Two attributes—user-defined (U0) and endian (E)—are defined by
the PowerPC embedded environment architecture (the PowerPC Book-E architecture also
supports these attributes).
The PowerPC architecture defines a memory-coherency attribute (M), but this attribute has
no effect when used in PPC405 systems.
Management of storage attributes depends on whether address translation is used to
access memory. In virtual mode, the page translation (TLB) entry for a virtual-memory
region defines the storage attributes (see
). In real mode,
the storage-attribute control registers are used to define the storage attributes (see
).
The following sections describe the function of each attribute.
Write Through (W)
The write-through storage attribute controls the caching policy of a memory region.
When the W attribute is cleared to 0, the memory region has a write-back caching policy.
Writes that hit the cache update the cacheline but they do not update system memory.
Writes that miss the cache allocate a new cacheline and update that line, but they do not
update system memory.
When the W attribute is set to 1, the memory region has a write-through caching policy.
Writes that hit the cache update both the cacheline and system memory. Writes that miss
the cache update system memory and do not allocate a new cacheline.
Caching Inhibited (I)
The caching-inhibited storage attribute controls the cacheability of a memory region. The
value of this attribute and its effect on memory depends on whether the memory access is
performed in virtual mode or real mode.
In virtual mode, a memory region is cacheable when the I attribute is cleared to 0. When
the I attribute is set to 1, the memory region is not cacheable. Non-cacheable memory
accesses bypass the cache and access system memory. It is considered a programming error
when a memory-access target is resident in the cache and the I attribute is set to 1. The
result of such an access are undefined.
The interpretation of this attribute is reversed in real-mode, which uses the data-cache
cacheability register (DCCR) and the instruction-cache cacheability register (ICCR). Here,
setting I to 1 enables cacheability and clearing I to 0 disables cacheability. See
, for more information.
Memory Coherency (M)
The memory-coherency storage attribute controls memory coherency in multiprocessor
environments. Because the PPC405x3 core does not provide hardware support for
multiprocessor memory coherency, setting or clearing the M storage attribute has no effect.
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