Xilinx Virtex-II Pro PPC405, Руководство пользователя

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464 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
R
loop:
stwu r 3,4( r 1) ! r 1= r 1+4, write ( r 3) to address in r 1.
addi r
3,
r
3,1 ! Increment data (
r
3=
r
3+1).
bdnz loop ! Repeat until done.
As the program executes, cachelines are fetched from system memory into the cache and
portions of the lines are overwritten with new data as specified by the program. The result
is shown in the following table. Because the addresses are write-back cacheable, system
memory is not updated. If an external device reads or writes the gray-shaded system-
memory locations, a loss of coherency occurs. This can be prevented only if software
flushes the affected lines from cache memory before the external device accesses system
memory.
To further illustrate coherency loss, assume normal cache operations cause the first two
cachelines to be replaced by unrelated data. Cacheline replacement updates system
memory as shown below. Here, fewer system-memory locations are not coherent (shaded
gray). An “
x ” indicates a replacement value in the cache unrelated to the program.
Next, assume an external device updates the words at system-memory addresses 0x100C–
0x1024, while at the same time a cacheline reload from 0x1010 occurs. This causes neither
system memory nor the cache to contain data expected by the programmer (gray-shaded
locations).
Coherency Loss Through Dual-Mapping
Some memory controllers support dual-mapping of physical-address ranges. With dual-
mapping, two address ranges are resolved as a single address range. For example, assume
System Memory Cache Memory
Address Data (Words) Address V D Line Data (Words)
1000 A9 2A 3A EB 1000 Yes Yes A9 00 01 02
1010 0C 93 EE A1 1010 Yes Yes 03 04 05 06
1020 EF 39 EB A6 1020 Yes Yes 07 08 09 0A
1030 3D 5F 8F 34 1030 Yes Yes 0B 5F 8F 34
System Memory Cache Memory
Address Data (Words) Address V D Line Data (Words)
1000 A9 00 01 02 x Yes x x x x x
1010 03 04 05 06 x Yes x x x x x
1020 EF 39 EB A6 1020 Yes Yes 07 08 09 0A
1030 3D 5F 8F 34 1030 Yes Yes 0B 5F 8F 34
System Memory Cache Memory
Address Data (Words) Address V D Line Data (Words)
1000 A9 00 01 FF x Yes x x x x x
1010 FE FD FC FB 1010 Yes No FE FD 05 06
1020 FA F9 EB A6 1020 Yes Yes 07 08 09 0A
1030 3D 5F 8F 34 1030 Yes Yes 0B 5F 8F 34