Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 453
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Memory-System Control
R
The following sections describe the six storage-attribute control registers in the PPC405.
Data-Cache Write-Through Register (DCWR)
The data-cache write-through register (DCWR) specifies real-mode caching policy (the W
storage attribute). Its format is shown in
Figure 5-7 . Each bit in the DCWR controls
whether a physical-memory region (as shown in Table 5-2 ) has a write-back or write-
through caching policy. This register controls only the data-cache caching policy. The
caching policy is not applicable to the instruction cache because writes into the instruction-
cache are not supported.
When a bit in the DCWR is cleared to 0, the specified memory region has a write-back
caching policy. Writes that hit the cache update the cacheline but they do not update
system memory. Writes that miss the cache allocate a new cacheline and update that line,
but they do not update system memory. When the bit is set to 1, the specified memory
region has a write-through caching policy. Writes that hit the cache update both the
cacheline and system memory. Writes that miss the cache update system memory, but they
do not allocate a new cacheline.
After a processor reset, all bits in the DCWR are cleared to 0. This establishes a write-back
caching policy for all real-mode memory.
The DCWR is a privileged SPR with an address of 954 (0x3BA) and can be read and written
using the
mfspr and mtspr instructions.
Table 5-2: Storage-Attribute Control-Register Address Ranges
Register Bit
Indexed
with EA
0:4
Address Range
Register Bit
Indexed
with EA
0:4
Address Range
0 0x0000_0000 to 0x07FF_FFFF 16 0x8000_0000 to 0x87FF_FFFF
1 0x0800_0000 to 0x0FFF_FFFF 17 0x8800_0000 to 0x8FFF_FFFF
2 0x1000_0000 to 0x17FF_FFFF 18 0x9000_0000 to 0x97FF_FFFF
3 0x1800_0000 to 0x1FFF_FFFF 19 0x9800_0000 to 0x9FFF_FFFF
4 0x2000_0000 to 0x27FF_FFFF 20 0xA000_0000 to 0xA7FF_FFFF
5 0x2800_0000 to 0x2FFF_FFFF 21 0xA800_0000 to 0xAFFF_FFFF
6 0x3000_0000 to 0x37FF_FFFF 22 0xB000_0000 to 0xB7FF_FFFF
7 0x3800_0000 to 0x3FFF_FFFF 23 0xB800_0000 to 0xBFFF_FFFF
8 0x4000_0000 to 0x47FF_FFFF 24 0xC000_0000 to 0xC7FF_FFFF
9 0x4800_0000 to 0x4FFF_FFFF 25 0xC800_0000 to 0xCFFF_FFFF
10 0x5000_0000 to 0x57FF_FFFF 26 0xD000_0000 to 0xD7FF_FFFF
11 0x5800_0000 to 0x5FFF_FFFF 27 0xD800_0000 to 0xDFFF_FFFF
12 0x6000_0000 to 0x67FF_FFFF 28 0xE000_0000 to 0xE7FF_FFFF
13 0x6800_0000 to 0x6FFF_FFFF 29 0xE800_0000 to 0xEFFF_FFFF
14 0x7000_0000 to 0x77FF_FFFF 30 0xF000_0000 to 0xF7FF_FFFF
15 0x7800_0000 to 0x7FFF_FFFF 31 0xF800_0000 to 0xFFFF_FFFF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 5-7: Data-Cache Write-Through Register (DCWR)