516
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 7:
Exceptions and Interrupts
R
Programmable-Interval Timer Interrupt (0x1000)
Interrupt Classification
•
Noncritical—return using the
rfi
instruction.
•
Asynchronous.
•
Precise.
Description
A programmable-interval timer exception is caused by a time-out on the programmable-
interval timer (PIT). A time-out occurs when:
1.
The current PIT contents are 1.
2.
The PIT is decremented. Decrementing the PIT when the current value is 1 can cause
the PIT to be loaded either with a value of 0, or cause a new non-zero value to be
automatically loaded.
When a time-out is detected, the processor sets the PIT-status bit in the timer-status register
(TSR[PIS]) to 1. At the beginning on the next clock cycle, the set TSR[PIS] bit causes the PIT
interrupt to occur. Using the
mtspr
instruction to clear the PIT to 0
does not
cause a PIT
interrupt.
This exception is persistent. To prevent repeated interrupts from occurring, the interrupt
handler must clear the exception status in TSR[PIS] before returning.
This interrupt is enabled only by setting both of the following:
•
The PIT-interrupt enable bit in the timer-control register (TCR[PIE]) must be set to 1.
•
The external-interrupt enable bit in the machine-state register (MSR[EE]) must be set
to 1.
If either TCR[PIE]
=
0 or MSR[EE]
=
0, a PIT interrupt does not occur. See
, for more information on the PIT, TCR, and TSR.
Affected Registers
The timer-status register (TSR) is also updated as a result of a PIT exception.
Register
Value After Interrupt
SRR0
Loaded with the effective address of the next-sequential instruction to be
executed at the point the interrupt occurs.
SRR1
Loaded with a copy of the MSR at the point the interrupt occurs.
SRR2
Not used.
SRR3
ESR
DEAR
MSR
[AP, APE, WE, EE, PR, FP, FE0, DWE, FE1, IR, DR]
←
0.
[CE, ME, DE]
←
Unchanged.
Register
Value After Exception
TSR
[PIS]
←
1.
All others are unchanged.
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