710
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 11:
Instruction Set
R
rfci
Return from Critical Interrupt
Description
This is a privileged instruction.
The MSR is loaded with the contents of SRR3. The contents of SRR2 are used as the next-
instruction address (NIA). Program control is transferred to the NIA. This instruction is
context synchronizing. Instructions fetched from the NIA use the new context loaded into
the MSR.
Pseudocode
(MSR
) ←
(SRR3)
Synchronize context
NIA
←
(SRR2)
Registers Altered
•
MSR.
Exceptions
•
Program—Attempted execution of this instruction from user mode.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is defined by the operating-environment architecture level (OEA) of the
the PowerPC embedded-environment architecture and the PowerPC Book-E architecture.
It is not defined by the PowerPC architecture, and is therefore not implemented by all
PowerPC processors.
rfci
XL Instruction Form
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
51
0
0
6
2
1
3
1
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