Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 487
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Maintaining Shadow-TLB Consistency
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modified, they must be saved prior to loading the replacement (new) pages. If the old
pages were not modified, the new pages can be loaded without saving the old pages.
• A limited number of page translations are kept in the UTLB. The remaining
translations must be stored in the page-translation table. When a translation is not
found in the UTLB (due to a miss), system software must decide which UTLB entry to
discard so that the missing translation can be loaded. It is desirable for system
software to replace infrequently used translations rather than frequently used
translations.
Solving the above problems in an efficient manner requires keeping track of page accesses
and page modifications. The PPC405 does not track page access and page modification in
hardware. Instead, system software can use the TLB-miss exceptions and the data-storage
exception to collect this information. As the information is collected, it can be stored in a
data structure associated with the page-translation table.
Page-access information is used to determine which pages should be kept in physical
memory and which are replaced when physical-memory space is required. System
software can use the valid bit in the TLB entry (TLBHI[V]) to monitor page accesses. This
requires page translations be initialized as not valid (TLBHI[V]
=
0) to indicate they have
not been accessed. The first attempt to access a page causes a TLB-miss exception, either
because the UTLB entry is marked not valid or because the page translation is not present
in the UTLB. The TLB-miss handler updates the UTLB with a valid translation
(TLBHI[V]
=
1). The set valid bit serves as a record that the page and its translation have
been accessed. The TLB-miss handler can also record the information in a separate data
structure associated with the page-translation entry.
Page-modification information is used to indicate whether an old page can be overwritten
with a new page or the old page must first be stored to a hard disk. System software can
use the write-protection bit in the TLB entry (TLBLO[WR]) to monitor page modification.
This requires page translations be initialized as read-only (TLBLO[WR]
=
0) to indicate they
have not been modified. The first attempt to write data into a page causes a data-storage
exception, assuming the page has already been accessed and marked valid as described
above. If software has permission to write into the page, the data-storage handler marks
the page as writable (TLBLO[WR]
=
1) and returns. The set write-protection bit serves as a
record that a page has been modified. The data-storage handler can also record this
information in a separate data structure associated with the page-translation entry.
Tracking page modification is useful when virtual mode is first entered and when a new
process is started.
Maintaining Shadow-TLB Consistency
The PPC405 TLBs are maintained by two different mechanisms: software manages the
UTLB and the processor manages the shadow TLBs. Software must ensure the shadow
TLBs remain consistent with the UTLB when updates are made to entries in the UTLB. If
software updates any field in a UTLB entry, it
must synchronize that update with the
shadow TLBs. Failure to properly synchronize the shadow TLBs can cause unexpected
behavior.
Synchronization occurs when the processor hardware replaces a shadow-TLB entry with
an updated entry from the UTLB. To force a replacement, software must invalidate the
shadow-TLB entry. This forces the MMU to read the modified entry from the UTLB the
next time it is accessed. The processor invalidates
all shadow-TLB entries when any of the
following context-synchronizing events occur:
• An isync instruction is executed.
• An sc instruction is executed.
• An interrupt occurs.
• An rfi or rfci instruction is executed.