Xilinx Virtex-II Pro PPC405, Руководство пользователя

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486 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 6: Virtual-Memory Management
R
Software reads and writes UTLB entries using the tlbre and tlbwe instructions,
respectively. These instructions specify an index (numbered 0 to 63) corresponding to one
of the 64 entries in the UTLB. The tag and data portions are read and written separately, so
software must execute two
tlbre or tlbwe instructions to completely access an entry. The
UTLB is searched for a specific translation using the
tlbsx
instruction.
tlbsx
locates a
translation using an effective address and loads the corresponding UTLB index into a
register.
Simplified mnemonics are defined for the TLB read and write instructions. See TLB-
Management Instructions , page 832 , for more information.
The tlbia instruction invalidates the entire contents of the UTLB. Individual entries are
invalidated using the tlbwe instruction to clear the valid bit in the tag portion of a TLB
entry (TLBHI[V]).
The tlbsync instruction performs no operation on the PPC405 because the processor does
not provide hardware support for multiprocessor memory coherency.
Recording Page Access and Page Modification
Software management of virtual-memory poses several challenges:
• In a virtual-memory environment, software and data often consume more memory
than is physically available. Some of the software and data pages must be stored
outside physical memory, such as on a hard drive, when they are not used. Ideally, the
most-frequently used pages stay in physical memory and infrequently used pages are
stored elsewhere.
• When pages in physical-memory are replaced to make room for new pages, it is
important to know whether the replaced (old) pages were modified. If they were
tlbsx TLB Search Indexed If a translation is found, r D is loaded with the index
of the UTLB entry for the page specified by EA. If a
translation is not found,
r D is undefined. The index
is used by the tlbre and tlbre instructions.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r D, r A, r B
tlbsx. TLB Search Indexed and Record If a translation is found, r D is loaded with the index
of the UTLB entry for the page specified by EA, and
CR0[EQ] is set to 1. If a translation is not found,
r D
is undefined and CR0[EQ] is cleared to 0. The index
is used by the
tlbre and tlbre instructions.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
tlbsync TLB Synchronize On the PPC405, this instruction performs no
operation. —
tlbwe TLB Write Entry r A contains an index value ranging from 0 to 63.
Part of the UTLB entry specified by the index in r A
is loaded with the value in r S. If WS
=
0, the tag
portion (TLBHI) is loaded from r S and the
TLBHI[TID] field is updated with the PID. If WS
=
1,
the data portion (TLBLO) is loaded from r S.
r S, r A,WS
Table 6-5: TLB-Management Instructions
Mnemonic Name Operation
Operand
Syntax