March 2002 Release
495
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
PPC405D5 Exceptions and Interrupts
R
1.
All previous instructions complete execution in the context they were issued
(privilege, protection, and address-translation mode).
2.
All previous instructions are completed to a point where they can no longer cause an
exception.
3.
The processor loads the MSR with the interrupted-program state from one of two
save/restore registers, depending on the instruction:
-
rfi
copies SRR1 into the MSR.
-
rfci
copies SRR3 into the MSR.
4.
Processor context is synchronized.
Both instructions are context synchronizing. The processor fetches and executes the
instruction at the return address in the interrupted-program context.
5.
The processor begins fetching and executing instructions from the interrupted
program:
-
Instructions are fetched from the address in SRR0 following completion of the
rfi
.
-
Instructions are fetched from the address in SRR2 following completion of the
rfci
.
Simultaneous Exceptions and Interrupt Priority
The PPC405 interrupt mechanism responds to exceptions serially. If multiple exceptions
are pending simultaneously, the associated interrupts occur in a consistent and predictable
order. Even though critical and noncritical exceptions use different save/restore register
pairs, simultaneous occurrences of these exceptions are also processed serially.
The PPC405 uses the interrupt priority shown in
for handling simultaneous
exceptions. Lower-priority interrupts occur ahead of
masked
higher-priority interrupts.
Table 7-2:
Interrupt Priority for Simultaneous Exceptions
Priority
Exception
Cause
1
Machine check—Data.
External bus error during data access.
2
Debug—Instruction-address compare.
Instruction-address compare (IAC) debug event.
3
Machine check—Instruction.
Attempted execution of an instruction for which an external bus error
occurred during instruction fetch.
4
Debug—Exception.
Exception (EDE) debug event.
Debug—Unconditional.
Unconditional (UDE) debug event.
5
Critical input
Critical-interrupt input signal is asserted.
6
Watchdog timer
Watchdog timer time-out.
7
Instruction TLB Miss
Attempted execution of an instruction from a memory address with no
valid, matching page translation loaded in the TLB (virtual mode only).
8
Instruction storage—No access.
In user mode, attempted execution of an instruction from a memory
address with no-access-allowed zone protection (virtual mode only).
9
Instruction storage—Non-executable.
Attempted execution of an instruction from a non-executable memory
address (virtual mode only).
Instruction storage—Guarded.
Attempted execution of an instruction from a guarded memory address.
Содержание Virtex-II Pro PPC405
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