Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 335
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
PPC405 Features
R
Central-Processing Unit
The PPC405 central-processing unit (CPU) implements a 5-stage instruction pipeline
consisting of fetch, decode, execute, write-back, and load write-back stages.
The fetch and decode logic sends a steady flow of instructions to the execute unit. All
instructions are decoded before they are forwarded to the execute unit. Instructions are
queued in the fetch queue if execution stalls. The fetch queue consists of three elements:
two prefetch buffers and a decode buffer. If the prefetch buffers are empty instructions
flow directly to the decode buffer.
Up to two branches are processed simultaneously by the fetch and decode logic. If a branch
cannot be resolved prior to execution, the fetch and decode logic predicts how that branch
is resolved, causing the processor to speculatively fetch instructions from the predicted
path. Branches with negative-address displacements are predicted as taken, as are
branches that do not test the condition register or count register. The default prediction can
be overridden by software at assembly or compile time. This capability is described further
in
Branch Prediction , page 370 .
The PPC405 has a single-issue execute unit containing the general-purpose register file
(GPR), arithmetic-logic unit (ALU), and the multiply-accumulate unit (MAC). The GPRs
consist of thirty-two 32-bit registers that are accessed by the execute unit using three read
ports and two write ports. During the decode stage, data is read out of the GPRs for use by
the execute unit. During the write-back stage, results are written to the GPR. The use of five
read/write ports on the GPRs allows the processor to execute load/store operations in
parallel with ALU and MAC operations.
Figure 1-3: PPC405 Organization
UG011_29_033101
I-Cache
Array
I-Cache
Controller
Instruction-Cache
Unit
D-Cache
Array
D-Cache
Controller
Data-Cache
Unit
Instruction
Shadow-TLB
(4-Entry)
Unified TLB
(64-Entry)
Data
Shadow-TLB
(8-Entry)
Execute Unit
32x32
GPR
ALU MAC
3-Element
Fetch Queue
Fetch
and
Decode
Logic
Timers
Debug
Logic
PLB Master
Read Interface
PLB Master
Read Interface
PLB Master
Write Interface
Data
OCM
Instruction
OCM
JTAG
Instruction
Trace
CPU MMU
Timers
and
Debug
Cache Units
External-Interrupt
Controller Interface