Xilinx Virtex-II Pro PPC405, Руководство пользователя

Страница: 537 / 562

March 2002 Release www.xilinx.com 845
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Instruction Performance
R
address dependencies (the next instruction is executed). These instructions execute in
one clock cycle.
• A known taken branch does not have condition dependencies (they are resolved) but
can have address dependencies. These instructions execute as follows:
-
When address dependencies are resolved, the instruction executes in one or two
cycles depending on where the branch instruction is in the pipeline when the
address is resolved. If the address is resolved early (at or before prefetch) it
executes in one cycle. If the address is resolved during decode, it executes in two
cycles.
- When address dependencies are not resolved, the instruction executes in two or
three cycles. This depends on the separation between the branch and the address-
calculation instructions. If the separation is one instruction, the branch executes in
two cycles. If there is no separation, the branch executes in three cycles.
• A predicted not taken branch has condition dependencies. These instructions execute as
follows:
-
If the prediction is correct, the branch executes in one cycle.
- If the prediction is incorrect, the instruction executes in two or three cycles. This
depends on the separation between the branch and conditional instructions. If the
separation is one instruction, the branch executes in two cycles. If there is no
separation, the branch executes in three cycles.
• A predicted taken branch has condition dependencies. These instructions execute as
follows:
-
If the prediction is correct, the branch executes in one or two cycles, depending on
where the branch instruction is in the pipeline when the prediction occurs. If the
instruction is predicted early (at or before prefetch) it executes in one cycle. If the
instruction is predicted during decode, it executes in two cycles.
- If the prediction is incorrect, the instruction executes in two or three cycles. This
depends on the separation between the branch and the condition-setting
instructions. If the separation is one instruction, the branch executes in two cycles.
If there is no separation, the branch executes in three cycles.
Multiplies
The PPC405 supports word multiplication and halfword multiplication. Multiply-
accumulate (MAC) instructions are also supported. All of these instructions use the same
multiplication hardware and are pipelined by the processor in the execution unit.
The time required by the processor to multiply two words depends on whether the first
operand is larger than the second. The processor reduces the number of cycles required to
perform a multiplication by automatically detecting which operand is smaller and
internally ordering them appropriately. The operand size is determined by examining the
number of bits involved in the sign-extension.
Issue-rate cycles and latency cycles are associated with the pipelining of multiply and
MAC instructions, as shown in
Table D-1 . Issue-rate cycles describe the number of cycles
required between operations before the multiplication hardware can accept a new
operation. Latency cycles describe the total number of cycles for the multiplication
hardware to perform the operation.
Under the conditions described below, a second multiply or MAC instruction can begin
execution before the first multiply or MAC instruction completes. When these conditions
are met, the issue-rate cycle numbers apply. Otherwise, the latency cycle numbers apply. A
multiply or MAC instruction can follow another multiply or MAC and still meet the
conditions that support the use of the issue-rate cycle numbers.