334
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 1:
Introduction to the PPC405
R
Special-Purpose Registers
The processor contains a number of 32-bit
special-purpose registers
(SPRs). SPRs provide
access to additional processor resources, such as the count register, the link register, debug
resources, timers, interrupt registers, and others. Most SPRs are accessed only by
privileged software, but a few, such as the count register and link register, are accessed by
all software. See
for more
information.
Machine-State Register
The 32-bit
machine-state register
(MSR) contains fields that control the operating state of the
processor. This register can be accessed only by privileged software. See
, for more information.
Condition Register
The 32-bit
condition register
(CR) contains eight 4-bit fields, CR0–CR7. The values in the CR
fields can be used to control conditional branching. Arithmetic instructions can set CR0
and compare instructions can set any CR field. Additional instructions are provided to
perform logical operations and tests on CR fields and bits within the fields. The CR can be
accessed by all software. See
, for more information.
Device Control Registers
The 32-bit
device control registers
(not shown) are used to configure, control, and report
status for various external devices that are not part of the PPC405 processor. Although the
DCRs are not part of the PPC405 implementation, they are accessed using the
mtdcr
and
mfdcr
instructions. The DCRs can be accessed only by privileged software. See the
for more information on implementing DCRs.
PPC405 Organization
As shown in
, the PPC405 processor contains the following elements:
•
A 5-stage pipeline consisting of fetch, decode, execute, write-back, and load write-
back stages
•
A virtual-memory-management unit that supports multiple page sizes and a variety
of storage-protection attributes and access-control options
•
Separate instruction-cache and data-cache units
•
Debug support, including a JTAG interface
•
Three programmable timers
The following sections provide an overview of each element.
Содержание Virtex-II Pro PPC405
Страница 1: ...R Volume 2 a PPC405 User Manual Virtex II Pro Platform FPGA Developer s Kit March 2002 Release...
Страница 14: ...322 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Preface R...
Страница 252: ...560 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 260: ...568 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 562: ...870 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
