Xilinx Virtex-II Pro PPC405, Руководство пользователя

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388 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
These instructions are used to move up to 32 consecutive bytes of data between memory
and the GPRs without concern for alignment. The instructions can be used for short moves
between arbitrary memory locations or for long moves between misaligned memory
fields. Performance of these instructions is degraded if the leading and/or trailing bytes
are not aligned on a word boundary (see
Performance Effects of Operand Alignment ,
page 353 for more information).
The immediate form of the instructions take the byte count, n , from the NB instruction
field. If NB=0, then n =32. The indexed forms take the byte count from XER[25:31]. Unlike
the immediate forms, if XER[25:31]=0, then n =0. For the lswx instruction, the contents of
r D are undefined if n =0.
The n bytes are loaded into and stored from registers beginning with the most-significant
register byte. For loads, any unfilled low-order register bytes are cleared to 0. The sequence
of registers loaded or stored wraps through r0 if necessary.
Figure 3-22 shows an example
of the string-instruction operation.
Table 3-23: Load and Store String Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
lswi Load String Word Immediate Register-indirect
EA
=
( r A|0)
r D, r A,NB
lswx Load String Word Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r D, r A, r B
stswi Store String Word Immediate Register-indirect
EA
=
( r A|0)
r S, r A,NB
stswx Store String Word Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r S, r A, r B