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March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
R
SGR register should be updated to mark memory as guarded only
where necessary. All remaining memory should not be guarded.
-
Initially, memory is big endian. If little-endian memory is accessed,
the SLER register must be updated appropriately.
-
User-defined storage attributes are disabled. If used by system
software, they must be enabled in the SU0R register.
2.
Configure the CCR0 register to specify how data and instructions are
loaded from system memory. Because this register is uninitialized, it is
important for software to update this register to maximize performance. If
possible:
-
Loads, stores, and instruction fetches should allocate cachelines on a
miss.
-
Prefetching should be enabled from cacheable and non-cacheable
memory.
-
The request sizes for non-cacheable instruction fetches and data
accesses should be set to the cache-line size (8 words).
3.
Configure the instruction cache to further improve instruction-fetch
performance.
-
The instruction cache must first be invalidated. The contents of the
cache are undefined following a reset and it is possible that some
cachelines are improperly marked valid. Cache invalidation
guarantees that false hits do not occur.
-
After reset, all memory is initialized as non-cacheable (the ICCR
register is cleared). Software should update this register as
appropriate to enable instruction caching.
4.
Configure the data cache to improve data-access performance.
-
Like the instruction cache, the data cache must first be invalidated.
The contents of the cache are undefined following a reset and it is
possible that some cachelines are improperly marked valid. Cache
invalidation guarantees that false hits do not occur.
-
The DCWR register must be initialized to specify which memory
locations use a write-back caching policy and which locations use a
write-through policy. This specification is required only for those
locations marked cacheable in the next step.
-
After reset, all memory is initialized as non-cacheable (the DCCR
register is cleared). Software should update this register as
appropriate to enable data caching.
5.
Configure the interrupt-handling mechanism. Internal exceptions are
always enabled. Up to this point it is important that initialization code not
cause an exception.
-
Interrupt handlers must be loaded into the appropriate system
memory locations.
-
The interrupt-handler table must be loaded with the “glue code” that
properly transfers control to the interrupt handlers following an
exception.
-
The EVPR register must be loaded with the base address of the
interrupt-handler table.
-
The timer resources must be initialized. If timers are not used, the
TCR register must be initialized to prevent the occurrence of timer
exceptions. Timer exceptions are enabled when critical and
noncritical external exceptions are enabled.
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