Xilinx Virtex-II Pro PPC405, Руководство пользователя

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524 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 8: Timer Resources
R
Time Base
The time base is a 64-bit incrementing counter supported by all PowerPC processors.
64 bits provide a long time period before
rolling over from 0xFFFF_FFFF_FFFF_FFFF to
0x0000_0000_0000_0000. At a clock rate of 300 MHz, for example, the time base increments
for about 1,950
years before rolling over. This makes it suitable for certain long-term timing
functions, such as time-of-day calculation. A time-base rollover is silent—it does not cause
an exception to timer event.
The 64-bit time base is implemented as two 32-bit registers. The time-base upper register
(TBU) holds time-base bits 0:31, and the time-base lower register (TBL) holds time-base bits
32:63.
Figure 8-2 shows the format of the time base.
The TBU and TBL registers are SPRs with user-mode read access and privileged-mode
write access. Reading the time-base registers requires use of the
move from time-base register
instruction. This instruction, shown in Table 8-1 , is similar to the move from SPR
instruction. The TBR number (TBRN) shown in the operand syntax column can be
specified as a decimal or hexadecimal value in the assembler listing. Within the instruction
opcode, this number is encoded using a
split-field notation (see Split-Field Notation ,
page 571 ).
Figure 8-1: PPC405 Timer Resources
UG011_47_033101
Time-Base Upper (TBU)
0 31
Time-Base Lower (TBL)
0 31
Programmable-Interval Timer Events Programmable-Interval Timer (PIT)
0 31
Zero Detect
2
21
2
17
2
13
2
9
Clocks (Bit 11)
Clocks (Bit 15)
Clocks (Bit 19)
Clocks (Bit 23)
2
29
2
25
2
21
2
17
Clocks (Bit 3)
Clocks (Bit 7)
Clocks (Bit 11)
Clocks (Bit 15)
Watchdog Timer Events
Fixed-Interval Timer Events
External Clock Source
64-Bit Time Base
0 31
TBU (Time Base [0:31])
0 31
TBL (Time Base [32:63])
Figure 8-2: Time-Base Register