Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 371
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Branch and Flow-Control Instructions
R
Algorithmically, a branch is predicted taken if:
((BO[0]
∧
BO[2])
∨
s )
=
1
where s is the sign bit of the displacement operand, if the instruction has a displacement
operand (bit 16 of the branch-conditional instruction encoding).
When the result of the above equation is 0, the branch is predicted not-taken and the
processor speculatively fetches instructions that sequentially follow the branch
instruction.
Examining the above equation, BO[0]
∧
BO[2]=1 only when the conditional branch tests
nothing, meaning the branch is always taken. In this case, the processor predicts the branch
as taken.
If the conditional branch tests anything (BO[0]
∧
BO[2]=0), s controls the prediction. In the
bclr x and bcctr x instructions, bit 16 ( s ) is reserved and always 0. In this case those
instructions are predicted not-taken.
Only the bc x instructions can specify a displacement value. The bc x instructions are
commonly used at the end of loops to control the number of times a loop is executed. Here,
the branch is taken every time the loop is executed except the last time, so a branch should
normally be predicted as taken. Because the branch target is at the beginning of the loop,
the branch displacement is negative and
s =1, so the processor predicts the branch as taken.
Forward branches have a positive displacement and are predicted not-taken.
When the y bit (BO[4]) is cleared to 0, the default branch prediction behavior described
above is followed by the processor. Setting the y bit to 1 reverses the above behavior. For
branch always encoding (BO[0], BO[2]), branch prediction cannot be reversed (no y bit is
recognized).
The sign of the displacement operand ( s ) is used as described above even when the target
is an absolute address. The default value for the y bit should be 0. Compilers can set this bit
if it they determine that the prediction corresponding to y =1 is more likely to be correct
than the prediction corresponding to y =0. Compilers that do not statically predict branches
should always clear the y bit.
Link-Register Stack
Some processor implementations keep a stack (history) of the LR values most recently
used by branch-and-link instructions. Those processors use this software-invisible stack to
predict the target address of nested-subroutine returns. Although the PPC405 processor
does not implement such a stack, the following programming conventions should be
followed so that software running on multiple PowerPC processors can benefit from this
stack.
In the following examples, let A , B , and Glue represent subroutine labels:
• When obtaining the address of the next instruction, use the following form of branch-
and-link:
bcl 20,31,$+4
• Loop counts:
Keep loop counts in the CTR, and use one of the branch-conditional instructions to
decrement the count and to control branching (for example, branching back to the start
of a loop if the decremented CTR value is nonzero).
• Computed “go to”, case statements, etc.:
Use the CTR to hold the branch-target address, and use the bcctr instruction with the
link register option disabled (LK=0) to branch to the selected address.
• Direct subroutine linkage, where A calls B and B returns to A :
- A calls B —use a branch instruction that enables the LR (LK=1).