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Appendix E:
PowerPC
®
6xx/7xx Compatibility
R
Processor-Version Register
The contents of the processor-version register (PVR) are implementation dependent.
Memory Management
The primary function of memory management is the translation of effective addresses to
physical addresses for instruction memory and data memory accesses. The secondary
function of memory management is to provide memory-access protection and memory-
attribute control. Memory management is handled by the memory-management unit
(MMU) in the processor.
Memory Translation
The PowerPC 6xx/7xx family manages memory translation by dividing the address space
into blocks, segments, and pages. The address-space divisions are characterized as follows:
•
Blocks specify large, contiguous memory regions (from 128KB to 256MB) with
common access protection and memory attributes. Blocks are defined using SPRs
called block address-translation (BAT) registers. The BAT registers are used by the
MMU to translate a 32-bit effective address within a BAT to a 32-bit physical address.
•
Segments are contiguous 256MB memory regions. Segment registers are used by the
MMU to translate a 32-bit effective address within a segment to a 52-bit virtual
address. 16 segment registers are available and they are accessed using move-to and
move-from segment register instructions.
•
Pages are contiguous 4KB memory regions. The MMU uses page-translation tables to
translate a 52-bit virtual address within a page to a 32-bit physical address. The page-
translation tables are created by software and stored in system memory. The processor
uses a translation look-aside buffer (TLB) to cache the most frequently used
translations. The processor manages many TLB functions in hardware, including
page-table walking and TLB entry replacement. TLB instructions are provided for
some software management, such as TLB invalidation.
If an effective address is not part of a memory region defined by a BAT, translation of that
address to a physical address is handled by the combined segment and page translation
mechanism. The effective address is translated first into a virtual address using the
segment registers. The resulting virtual address is translated to a physical address using
the page tables.
The PowerPC 40x family manages memory translation by dividing the address space into
pages. BAT and segment translation are not supported. Page translation in the PowerPC
40x family has the following characteristics:
•
Pages are contiguous, variable-sized memory regions. Page sizes can vary from 1KB
to 16MB.
•
Page-translation tables are created by software and stored in system memory. The
most frequently used translations are cached in the TLB. TLB management is the
responsibility of software, not hardware.
•
The MMU uses the page-translation tables to translate a 40-bit virtual address to a 32-
bit physical address. The 40-bit virtual address is the combination of the 32-bit
29
Reserved
PM—Performance Monitor Marked Mode
30
RI—Recoverable Exception
31
LE—Little-Endian Mode Enable
Table E-3:
Comparison of MSR Bit Definitions
MSR Bit
PowerPC 40x Family
PowerPC 6xx/7xx Family
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