March 2002 Release
455
Virtex-II Pro™ Platform FPGA Documentation
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Memory-System Control
R
Storage Guarded Register (SGR)
The storage guarded register (SGR) specifies guarded memory in real-mode (the G storage
attribute). Its format is shown in
. Each bit in the SGR controls whether a
physical-memory region (as shown in
) is guarded against speculative accesses.
This register affects instruction memory only. Speculative loads are not performed on the
PPC405, so guarding data memory has no effect. See
for more information.
When a bit in the SGR is cleared to 0, the specified memory region is not guarded and
speculative accesses from the memory region can occur. When the bit is set to 1, the
specified memory region is guarded and speculative accesses are not permitted.
After a processor reset, all bits in the SGR are set to 1. This establishes all of real-mode
memory as guarded.
The SGR is a privileged SPR with an address of 953 (0x3B9) and can be read and written
using the
mfspr
and
mtspr
instructions.
Storage User-Defined 0 Register (SU0R)
The storage user-defined 0 register (SU0R) specifies the implementation-dependent
behavior of real-mode memory accesses (the U0 storage attribute). Its format is shown in
. Some embedded-system implementations use the SU0R to identify physical
memory regions (as shown in
) containing compressed instructions. In those
implementations, memory regions with U0
=
1 contain compressed instructions and
memory regions with U0
=
0 contain uncompressed instructions.
System software can use the U0 storage attribute to implement real-mode write protection.
Writes to memory regions with U0
=
1 cause a data-storage exception if the U0 exception
condition is enabled. This exception condition is enabled by setting the U0-exception
enable bit (U0XE) in the CCR0 register to 1 (see
When CCR0[U0XE]
=
0, writes to physical-memory locations do not cause an exception
when the corresponding SU0R bit is set. See
Data-Storage Interrupt (0x0300)
for
information on the U0 exception condition.
After a processor reset, all bits in the SU0R are cleared to 0.
The SU0R is a privileged SPR with an address of 956 (0x3BC) and can be read and written
using the
mfspr
and
mtspr
instructions.
Storage Little-Endian Register (SLER)
The storage little-endian register (SLER) specifies the byte ordering for real-mode memory
accesses (the E storage attribute). Its format is shown in
. Each bit in the SLER
controls whether a physical-memory region (as shown in
) is accessed using big-
endian or little-endian byte ordering. See
for more information
on big-endian and little-endian memory accesses.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 5-10:
Storage Guarded Register (SGR)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 5-11:
Storage User-Defined 0 Register (SU0R)
Содержание Virtex-II Pro PPC405
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