Xilinx Virtex-II Pro PPC405, Руководство пользователя

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444 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
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If a cache miss occurs or if the data address is not cacheable, the DCU sends the data-
address request to system memory over the processor local bus (PLB). Store misses to
write-back memory and all load misses cause a cacheline fill. The size of all cacheline fill
requests over the PLB is 32 bytes. The request size for a store to write-through memory
(cache hit and cache miss) is one word (four bytes). The request size for a non-cacheable
data access is programmable using the CCR0 register (see
Core-Configuration Register ,
page 459 ). Cacheline fills are always completed (never aborted) even if the processor does
not require any other bytes in the line. As data is received by the DCU from the PLB, it is
placed in the fill buffer.
During a cacheline fill, the DCU requests the target data (load or store) first. However, the
order data is returned depends on the design of the PLB device that handles the request
(typically a memory controller). When the DCU receives target load data, it is forwarded
immediately to the GPR over the bypass path. When the DCU receives target store data, it
is immediately replaced by the GPR source value using the bypass path. The remaining
data is received from the PLB and placed in the fill buffer. Subsequent loads and stores
access the fill buffer if the data is present in the buffer. The data cacheline is loaded with the
fill-buffer contents after all data are received.
If a cacheline fill replaces a dirty (modified) cacheline, the processor causes a cacheline flush
to occur prior to loading the cacheline from the fill buffer. A cacheline flush updates system
memory with the modified data from the cache. All 32 bytes in a cacheline are written
sequentially to system memory over the PLB, including unmodified bytes.
Data Cacheability Control
Control of data cacheability depends on the address-translation mode:
• Real mode
• Virtual mode
Real Mode
In real mode, the data-cache cacheability register (DCCR) specifies which physical-
memory regions are cacheable. See
Data-Cache Cacheability Register (DCCR) , page 454 ,
for more information.
After a processor reset, the processor operates in real mode and all physical-memory
regions are marked as non-cacheable (all DCCR bits are cleared to 0). Prior to specifying
memory regions as cacheable, software must invalidate all data-cache congruence classes
by executing the
dccci instruction once for each class (see Cache Instructions , page 456 , for
information on this instruction). After the congruence classes are invalidated, the DCCR
can be configured.
Virtual Mode
In virtual mode, the storage-attribute fields in the page-translation look-aside buffer entry
(TLB entry) specify which virtual-memory regions are cacheable. See
Storage-Attribute
Fields , page 478 , for more information.
Data-Cache Write Policy
Cacheable data can be written to the data cache using two write policies:
• Write-back caching
• Write-through caching
Write-Back Caching
In a write-back caching policy, the data cache is updated by a write hit but system memory
is not updated. A write miss causes the cache to allocate a new cacheline and update that
line—system memory is not updated.
Write-back caching can improve system performance by minimizing processor local bus
activity. Write-back cachelines are only written to memory during cacheline replacement