454
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 5:
Memory-System Management
R
Data-Cache Cacheability Register (DCCR)
The data-cache cacheability register (DCCR) specifies real-mode data-memory
cacheability (the I storage attribute). Its format is shown in
. Each bit in the
DCCR controls whether a physical-memory region (as shown in
) is cacheable in
the data cache.
When a bit in the DCCR is cleared to 0, the specified memory region is not cacheable.
Memory accesses bypass the data cache and access main memory. It is considered a
programming error if a memory address is cached by the data cache when the
corresponding bit in the DCCR is cleared to 0. The result of such an access are undefined.
When the bit is set to 1, the specified memory region is cacheable, and its caching policy is
governed by the DCWR register.
After a processor reset, all bits in the DCCR are cleared to 0, indicating that physical
memory is not cacheable by the data cache. Prior to specifying memory regions as
cacheable, software must invalidate all data-cache congruence classes by executing the
dccci
instruction once for each class (see
for more
information). After the congruence classes are invalidated, the DCCR can be configured.
The interpretation of the I attribute is reversed in virtual-mode when using page
translations (TLB entries) to specify cacheability. See
for
more information.
The DCCR is a privileged SPR with an address of 1018 (0x3FA) and can be read and written
using the
mfspr
and
mtspr
instructions.
Instruction-Cache Cacheability Register (ICCR)
The instruction-cache cacheability register (ICCR) specifies real-mode instruction-memory
cacheability (the I storage attribute). Its format is shown in
. Each bit in the ICCR
controls whether a physical-memory region (as shown in
) is cacheable in the
instruction cache.
When a bit in the ICCR is cleared to 0, the specified memory region is not cacheable.
Memory accesses bypass the instruction cache and access main memory. It is considered a
programming error if a memory address is cached by the instruction cache when the
corresponding bit in the ICCR is cleared to 0. The result of such an access are undefined.
When the bit is set to 1, the specified memory region is cacheable.
After a processor reset, all bits in the ICCR are cleared to 0, indicating that physical
memory is not cacheable by the instruction cache. Prior to specifying memory regions as
cacheable, software must execute the
iccci
instruction, which invalidates the entire
instruction cache (see
for more information). After the cache
is invalidated, the ICCR can be configured.
The polarity of the I attribute is opposite in virtual-mode when using page translations
(TLB entries) to specify cacheability. See
for more
information.
The ICCR is a privileged SPR with an address of 1019 (0x3FB) and can be read and written
using the
mfspr
and
mtspr
instructions.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 5-8:
Data-Cache Cacheability Register (DCCR)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 5-9:
Instruction-Cache Cacheability Register (ICCR)
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