Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 535
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
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Chapter 9
Debugging
The PPC405 debugging resources can be used by system software and external hardware
to implement software debug and trace-capture tools (collectively referred to as
debuggers ).
These resources provide the following capabilities:
• Debug modes that support various debug tools and debug tasks commonly used in
embedded-systems development.
• A debug exception (vector offset 0x2000) for use by debuggers when debug events
occur.
• A variety of debugging functions (not all functions are available from all debug
modes):
-
Debug Events —Several types of debug events are available from the various
debug modes. When detected, debug events can cause an interrupt or stop the
processor, depending on the debug mode.
- Trap Instructions —The trap instructions ( tw and twi ) can be used to set software
breakpoints that cause debug events rather than program interrupts.
- Halt —An external debug signal can be used to halt (stop) the processor. No
instructions are executed during a halt, but processor registers can be read and
written using the JTAG port. Execution resumes when the external halt signal is
de-asserted.
- Stop —Stop can be used to halt the processor using the JTAG port rather than the
external halt signal. No instructions are executed during a halt, but processor
registers can be read and written using the JTAG port.
- Instruction Step —Using the JTAG port, the processor can be stopped and single-
stepped one instruction at a time.
- Instruction Stuff —Using the JTAG port, the processor can be stopped and
instructions can be inserted (stuffed) into the processor and executed. The
instructions do not replace existing instruction.
- Freeze Timers —The JTAG port or a debug-control register can be used to control
the PPC405 timer resources. The timers can be frozen (stopped) completely, frozen
only for the duration of debug events, or left running.
- Reset —A processor, chip, or system reset can be forced using the JTAG port, a
debug-control register, or external signalling.
• Control registers used to manage the debug modes and functions.
• Status registers used to report debug information.
• Status reporting through the JTAG port, including:
-
Execution Status —Indicates whether the processor is stopped, waiting, or running.
- Exception Status —Indicates the status of pending synchronous exceptions.
- Most Recent Reset —Indicates the cause of the most-recent reset.
• A debug interface (JTAG) and a trace interface for connecting external hardware and
software debug tools.