March 2002 Release
527
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Timer-Event Registers
R
stw
r
x, posix_tb
! Update record of last time-base value.
stw
r
y, p4
Timekeeping software can use the posix_sec value to compute the current date and time by
adding it to the fixed reference time.
Varying the Update Frequency
Time-of-day computations require a comparison between the current time-base value and
a fixed-reference time. This reference time is valid only when the time-base update
frequency remains fixed. Many embedded systems change the time-base update frequency
periodically. Changes are often initiated by system software, but hardware can also cause
a frequency change (for example, a low-power mode that is initiated by a sudden power
failure). When the frequency changes, a mechanism must be provided to the time-of-day
calculation routine notifying it of the change. If the change is software initiated, a system
call to the calculation routine can be used. If the change is hardware initiated, an external
interrupt can be used.
When the time-of-day calculation routine is called, it must compute new reference values.
This involves the following:
•
Saving the time-base value at the point the frequency is changed.
•
Computing and saving the current time-of-day using the old update frequency and
the saved time-base value.
•
Computing and saving a new value for ticks_per_sec.
Later calls to compute the time-of-day can use the updated variables along with the
current time-base value to calculate the correct time.
Timer-Event Registers
Three PPC405 registers are defined for managing timer-event interrupts:
•
Programmable-interval timer register.
•
Timer-control register.
•
Timer-status register.
A description of each register is provided in the following sections.
Programmable-Interval Timer Register
The programmable-interval timer (PIT) register is a 32-bit decrementing counter that is
clocked at the same frequency as the time-base register. It can be used by software to cause
a PIT interrupt after a variable-length time period elapses.
the PIT register.
The PIT is a privileged SPR with an address of 987 (0x3DB). It is read and written using the
mfspr
and
mtspr
instructions.
When the PIT contains a value of 1 and is decremented, a PIT event occurs. A PIT event can
be used to cause a PIT interrupt as described in
Programmable-Interval Timer Events
. Auto-reload mode controls the state of the PIT register when it contains a value
of 1 and is decremented, as follows:
•
In auto-reload mode, the PIT is reloaded with the last value loaded by an
mtspr
instruction. In this mode, the PIT never contains a value of 0. Auto-reload mode is
enabled by setting the auto-reload enable bit in the timer-control register
0
31
Time remaining to PIT event
Figure 8-3:
Programmable-Interval Timer Register (PIT)
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