472
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 6:
Virtual-Memory Management
R
physical address is identical to the effective address and the processor uses the EA to
access physical memory. After a processor reset, the processor operates in real mode. Real
mode can also be enabled independently for instruction fetches and data accesses by
clearing the appropriate bits in the MSR:
•
Clearing the
instruction-relocate
bit (MSR[IR]) to 0 disables instruction-address
translation. Instruction fetches from physical memory are performed in real mode
using the effective address.
•
Clearing the
data-relocate
bit (MSR[DR]) to 0 disables data-address translation.
Physical-memory data accesses (loads and stores) are performed in real mode using
the effective address.
Real mode does not provide system software with the level of memory-management
flexibility available in virtual mode. Storage attributes are associated with real-mode
memory but access protection is limited (the U0 storage attribute can be used for write
protection). Implementation of a real-mode memory manager is more straightforward
than a virtual-mode memory manager. Real mode is often an appropriate solution for
memory management in simple embedded environments.
See
Storage-Attribute Control Registers
, for more information on real-mode
memory control.
Virtual Mode
In virtual mode, the processor translates an EA into a physical address using the process
shown in
. Virtual mode can be enabled independently for instruction fetches
and data accesses by setting the appropriate bits in the MSR:
•
Setting the instruction-relocate bit (MSR[IR]) to 1 enables address translation (virtual
mode) for instruction fetches.
•
Setting the data-relocate bit (MSR[DR]) to 1 enables address translation (virtual mode)
for data accesses (loads and stores).
Figure 6-1:
Virtual-Mode Address Translation
UG011_37_021302
32-Bit Effective Address
0
Effective Page Number
Offset
n
31
0
PID
24
31
Translation Look-Aside
Buffer (TLB) Look-Up
0
Effective Page Number
Offset
n+8
39
PID
8
40-Bit Virtual Address
0
Real Page Number
Offset
n
31
32-Bit Physical Address
Process ID Register
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