Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 543
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
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The IAC n registers are privileged SPRs with the following addresses:
• IAC1—1012 (0x3F4).
• IAC2—1013 (0x3F5).
• IAC3—948 (0x3B4).
• IAC4—949 (0x3B5).
These registers are read and written using the mfspr and mtspr instructions.
Data Address-Compare Registers
The PPC405 contains two 32-bit data address-compare registers, DAC1 and
DAC2. These registers are used by the data address-compare debug event.
Figure 9-5 shows the format of the DAC n registers. Any byte-aligned data
effective-address can be loaded in these registers.
The DAC n registers are privileged SPRs with the following addresses:
• DAC1—1014 (0x3F6).
• DAC2—1015 (0x3F7).
These registers are read and written using the mfspr and mtspr instructions.
Data Value-Compare Registers
The PPC405 contains two 32-bit data value-compare registers, DVC1 and
DVC2. These registers are used by the data value-compare debug event.
Figure 9-5 shows the format of the DVC
n
registers. Any data value can be
loaded in these registers.
The DVC n registers are privileged SPRs with the following addresses:
• DVC1—950 (0x3B6).
• DVC2—951 (0x3B7).
These registers are read and written using the mfspr and mtspr instructions.
Debug Events
A debug event occurs when a debug condition is detected by the processor.
Debug conditions are enabled using the debug-control registers (DBCR0 and
DBCR1). Some of the debug events make use of one or more of the compare
registers (IAC
n , DAC n , and DVC n ). Depending on the debug mode, a debug
event causes the following to occur:
0 29 30 31
Instruction Effective-Address 00
Figure 9-4: Instruction Address-Compare Registers (IAC1–IAC4)
0 31
Data Effective-Address
Figure 9-5: Data Address-Compare Registers (DAC1, DAC2)
0 7 8 15 16 23 24 31
Data-Value Byte 0 Data-Value Byte 1 Data-Value Byte 2 Data-Value Byte 3
Figure 9-6: Data Value-Compare Registers (DVC1, DVC2)