448
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 5:
Memory-System Management
R
cache flushes. The coherency and ordering of these memory accesses are influenced by the
processor implementation, the memory system design, and software execution.
Memory Coherency
Coherency describes the ordering of reads from and writes to a single memory location. A
memory system is
coherent
when the value read from a memory address is always the last
value written to the address. In a system where all devices read and write from a single,
shared system memory, memory is always coherent. In systems with memory-caching
devices, maintaining coherency is less straightforward. For example, a processor cache can
contain a more recent value for a memory location than system memory. The memory
system is coherent only when a mechanism is provided to ensure a device receives the
cached value rather than the system-memory value when read.
The PPC405
does not
support memory-coherency management in hardware. Certain
situations exist where coherency can be lost between system memory and the processor
caches. On the PPC405, these situations require software management of memory
coherency. See
Software Management of Cache Coherency
, for more
information.
Atomic Memory Access
An access is
atomic
if it is always performed in its entirety with no software-visible
fragmentation. Only the following single-register accesses are guaranteed to be atomic:
•
Byte accesses.
•
Halfword accesses aligned on halfword boundaries.
•
Word accesses aligned on word boundaries.
No other access is guaranteed to be atomic, particularly the following:
•
Load and store operations using unaligned operands.
•
Accesses resulting from execution of the
lmw
,
stmw
,
lswi
,
lswx
,
stswi
, or
stswx
instructions.
•
Accesses resulting from execution of cache-management instructions.
The
lwarx
/
stwcx.
instruction combination can be used to perform an atomic memory
access. The
lwarx
instruction is a load from a word-aligned memory location that has two
side effects:
•
A reservation for a subsequent
stwcx.
instruction is created.
•
The memory coherence mechanism is notified that a reservation exists for the
memory location accessed by the
lwarx
.
The
stwcx.
instruction conditionally stores to a word-aligned memory location based on
the existence of a reservation created by
lwarx
. See
,
for more information on using these instructions.
Ordering Memory Accesses
The PowerPC architecture specifies a weakly-consistent memory model for shared-
memory multiprocessor systems. The order a processor performs memory accesses, the
order those accesses complete in memory, and the order those accesses are viewed as
occurring by another processor can all differ. This model provides an opportunity for
significantly improved performance over a model applying stronger consistency rules.
However, the responsibility for memory-access ordering is placed on the programmer.
When a program requires strict access ordering for proper execution, the programmer
must insert the appropriate ordering or synchronizing instructions into the program. The
PowerPC architecture provides the ability to enforce memory-access ordering among
multiple programs that share memory. Similar means are provided for programs that share
memory with other hardware devices, such as I/O devices. These are:
Содержание Virtex-II Pro PPC405
Страница 1: ...R Volume 2 a PPC405 User Manual Virtex II Pro Platform FPGA Developer s Kit March 2002 Release...
Страница 14: ...322 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Preface R...
Страница 252: ...560 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 260: ...568 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 562: ...870 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
