Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 463
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Software Management of Cache Coherency
R
mtspr CCR0, r N ! Update CCR0.
isync ! Refetch instructions under new processor context.
! Restore MSR to original value.
mtmsr r M
Modifications to CCR0[CIS] and CCR0[CWS] do not require special treatment.
Software Management of Cache Coherency
The PPC405 does not support memory-coherency management in hardware. This section
describes the situations that can cause a loss of memory coherency and the steps software
must take to prevent such loss.
How Coherency is Lost
Generally, coherency is lost when software shares cacheable memory with external
devices. When a memory address is cached, the potential for losing memory coherency
exists each time the address is accessed by any external device in the system. If a device
reads cacheable system-memory, it can receive incorrect data. This occurs when modified
data resides in write-back cachelines. Such data is not stored to system memory until the
modified line is replaced by another line or until it is stored explicitly by a cache-control
instruction. The use of write-through cachelines does not completely solve the problem.
When an external device updates a cacheable system-memory location, copies present in
the cache are not updated.
For example, when a DMA controller reads and writes cacheable system memory,
coherency can be lost because:
• The processor does not automatically supply the DMA controller with the latest copy
of data from the cache.
• The processor does not update cached locations with the latest copy written to system
memory by the DMA controller.
To illustrate how coherency can be lost, consider the initial state of system memory and the
contents of cache memory shown in the following table. For simplicity, the example uses a
cacheline size of 16 bytes rather than 32 bytes. Each data element in the table represents a
word (four bytes), although for clarity only byte values are shown. A row in the system-
memory portion and cache-memory portion of the table each contain 16 data bytes. The
“V” column indicates whether the cacheline is valid and the “D” column indicates whether
the line data is dirty (modified). A “—” in the cache-memory portions indicates a don’t
care.
This example assumes write-back caching is enabled for all system-memory addresses
represented in the above table (0x1000–0x103F). The following program is executed,
updating the data words in addresses 0x1004–0x1030:
li r 1,0x1004-4 ! Start at address 0x1004.
li r
2,12 ! Fill 12 words.
mtctr r 2 ! Initialize counter.
li r 3,0 ! Initialize data to zero.
System Memory Cache Memory
Address Data (Words) Address V D Data (Words)
1000 A9 2A 3A EB — No No — — — —
1010 0C 93 EE A1 — No No — — — —
1020 EF 39 EB A6 — No No — — — —
1030 3D 5F 8F 34 — No No — — — —