March 2002 Release
443
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Memory-System Organization
R
to the same physical-page number (RA
0:19
). Both effective-page numbers (0x8888_8 and
0xFFFF_F) are translated into the physical-page number 0x4444_4. The effective-page
offset (0x000) is not translated and is used as the physical-page offset (RA
20:31
=
EA
20:31
).
The ICU uses RA
0:21
as the tag and EA
19:26
as the index when accessing the instruction
cache. Overlap between tag and index exists in the bit range 19:21. However, only EA
19
is
used to both index the cache and translate part of the physical tag (EA
20:21
is not used to
translate 4 KB virtual pages). In this example, a synonym exists because the effective
addresses differ in EA
19
. The two virtual addresses select different cachelines, even though
the address translation mechanism maps them to a single physical address.
Because the PPC405 supports variable page sizes, different high-order EA bits are used to
translate pages. The result is that synonyms can occur to varying degrees based on page
size:
•
1 KB pages—three bits (EA
19:21
) are used in indexing and tag comparison, resulting in
as many as eight synonyms
•
4 KB pages—one bit (EA
19
) is used in indexing and tag comparison, resulting in two
possible synonyms
The following two options are available for preventing cache synonyms:
•
Avoid mapping multiple virtual pages into a single physical page when using 1 KB or
4 KB pages sizes
•
Use pages sizes of 16 KB or greater if multiple virtual pages must be mapped into a
single physical page
Data-Cache Operation
shows how data flows between the data-cache unit (DCU) and the general-
purpose registers.
All data-load requests and data-store requests are handled by the DCU. If a data address is
cacheable, the DCU examines the data cache for a hit. A hit causes the cacheline to be read
from the data cache and loaded into the line buffer. For a load hit, the data value is read
from the line buffer and written to a GPR. For a store hit, the data value is read from the
GPR and written to the line buffer and the line buffer is stored back into the data cache. The
data cache supports byte writeability to improve the performance of byte and halfword
stores. Load hits and store hits can be completed in one clock cycle.
Figure 5-6:
Data Flow to/from the Data-Cache Unit
Fill Buffer
Line Buffer
UG011_44_033101
Processor Local Bus
D-Cache
Array
D-Cache
Tags
GPRs
Data
Bypass
Data-Request
Address
Data Address
DCU
Flush
Содержание Virtex-II Pro PPC405
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