March 2002 Release
461
Virtex-II Pro™ Platform FPGA Documentation
1-800-255-7778
Cache Control
R
The CCR0 is a privileged SPR with an address of 947 (0x3B3) and can be read and written
using the
mfspr
and
mtspr
instructions.
PLB-Request Priority
shows the encoding of the 2-bit PLB-request priority signal. This signal is sent
from a PLB master to a PLB arbiter indicating the priority of the master request. The arbiter
uses these signals along with priority signals from other masters to determine which
request should be granted. The PPC405 ICU and DCU are both PLB masters, and software
can control their respective PLB-request priority using CCR0[IPP] and CCR0[DPP1].
CCR0 Programming Guidelines
Several fields in CCR0 affect the instruction-cache and data-cache operation. Severe
problems can occur—including a processor hang—if these fields are modified while the
cache unit is involved in a PLB operation. To prevent problems, certain code sequences
must be followed when modifying the CCR0 fields.
The first code example (Sequence 1) can be used to alter any field within CCR0. Use of this
sequence is
required
when altering either CCR0[IPP] or CCR0[FWOA], both of which affect
instruction-cache operation. In this and the following example, registers
r
N,
r
M,
r
X, and
r
Z
are any available GPRs.
22
NCRS
Non-Cacheable Request Size
0—Request size is four words.
1—Request size is eight words.
Specifies the number of instructions requested from non-cacheable
memory when an instruction fetch or prefetch occurs. (Requests to
cacheable memory are always eight words.)
23
FWOA
Fetch Without Allocate
0—Allocate.
1—Do not allocate.
When this bit is set to 1, an instruction-fetch miss behaves like a
non-cacheable fetch and does allocate a data cacheline. When
cleared to 0, fetch misses from cacheable memory allocate a data
cacheline.
24:26
Reserved
27
CIS
Cache-Information Select
0—Information is cache data.
1—Information is cache tag.
This bit is used by the
dcread
and
icread
instructions, and specifies
whether cache-data or cache-tag information is loaded into the
destination register. See
for more
information.
28:30
Reserved
31
CWS
Cache-Way Select
0—Cache way is A.
1—Cache way is B.
This bit is used by the
dcread
and
icread
instructions, and identifies
the cache way (A or B) from which the cache information specified
by CCR0[CIS] is read. The information is loaded into the
destination register. See
for more
information.
Table 5-6:
Core-Configuration Register (CCR0) Field Definitions
(Continued)
Bit
Name
Function
Description
Table 5-7:
PLB-Request Priority Encoding
Bit 0
Bit 1
Definition
0
0
Lowest PLB-request priority.
0
1
Next-to-lowest PLB-request priority.
1
0
Next-to-highest PLB-request priority.
1
1
Highest PLB-request priority.
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