328
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 1:
Introduction to the PPC405
R
Operating Environment
The operating environment describes features of the architecture that enable operating
systems to allocate and manage storage, to handle errors encountered by application
programs, to support I/O devices, and to provide operating-system services. It specifies
the resources and mechanisms that require privileged access, including the memory-
protection and address-translation mechanisms, the exception-handling model, and
privileged timer resources.
summarizes the operating-environment features of
the PowerPC embedded-environment architecture.
Table 1-2:
Operating-Environment Features of the PowerPC Embedded-Environment Architecture
Operating
Environment
Features
Register model
•
Privileged special-purpose registers (SPRs) and instructions for accessing those
registers
•
Device control registers (DCRs) and instructions for accessing those registers
Storage model
•
Privileged cache-management instructions
•
Storage-attribute controls
•
Address translation and memory protection
•
Privileged TLB-management instructions
Exception model
•
Dual-level interrupt structure supporting various exception types
•
Specification of interrupt priorities and masking
•
Privileged SPRs for controlling and handling exceptions
•
Interrupt-control instructions
•
Specification of how partially executed instructions are handled when an interrupt
occurs
Debug model
•
Privileged SPRs for controlling debug modes and debug events
•
Specification for seven types of debug events
•
Specification for allowing a debug event to cause a reset
•
The ability of the debug mechanism to freeze the timer resources
Time-keeping model
•
64-bit time base
•
32-bit decrementer (the programmable-interval timer)
•
Three timer-event interrupts:
-
Programmable-interval timer (PIT)
-
Fixed-interval timer (FIT)
-
Watchdog timer (WDT)
•
Privileged SPRs for controlling the timer resources
•
The ability to freeze the timer resources using the debug mechanism
Synchronization
requirements
•
Requirements for special registers and the TLB
•
Requirements for instruction fetch and for data access
•
Specifications for context synchronization and execution synchronization
Reset and initialization
requirements
•
Specification for two internal mechanisms that can cause a reset:
-
Debug-control register (DBCR)
-
Timer-control register (TCR)
•
Contents of processor resources after a reset
•
The software-initialization requirements, including an initialization code example
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