438
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 5:
Memory-System Management
R
Memory-System Features
The PPC405 memory system supports the following features:
•
Separate 64-bit instruction and 64-bit data interfaces to the processor local bus (PLB).
•
Separate 64-bit instruction and 32-bit data interfaces to the on-chip memory (OCM).
•
Single-cycle access to the OCM (depending on how much BRAM is connected to the
processor), matching the access time for cache hits.
•
Independent, programmable PLB-request priority for the instruction and data
interfaces.
•
Support for big-endian and little-endian memory systems.
•
Support for unaligned load and store operations.
•
Separate instruction and data caches (Harvard cache model) with the following
characteristics:
-
16 KB 2-way set-associative cache arrays.
-
32-byte cachelines.
-
Programmable line allocation for instruction fetches, data loads, and data stores.
-
Non-blocking access for cache hits during line fills (the data cache is also non-
blocking during cache flushes).
-
Critical-word bypass for cache misses.
-
Programmable PLB request size for non-cacheable memory requests.
-
A complete set of cache-control instructions.
•
Specific features supported by the instruction-cache include:
-
A virtually-indexed and physically-tagged cache array.
-
Programmable address pipelining and prefetching for cache misses and non-
cacheable requests.
-
Buffering of up to eight non-cacheable instructions in the fill buffer.
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Support for non-cacheable hits into the fill buffer.
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Flash invalidate—one instruction invalidates the entire cache.
•
Specific features supported by the data-cache include:
-
A physically-indexed and physically-tagged cache array.
-
Flexible control over write-back and write-through strategies for each cacheable
memory region.
-
Address pipelining for cache misses.
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Buffering of up to 32 bytes of data in the fill buffer.
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Support for non-cacheable hits into the fill buffer.
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Handling of up to two pending cacheline flushes.
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Handling of up to three pending stores before causing a pipeline stall.
Cache Organization
The PPC405 contains an instruction-cache unit and a data-cache unit. Each cache unit
contains a 16 KB, 2-way set-associative cache array, plus control logic for managing cache
accesses. The caches contain copies of the most frequently used instructions and data and
can typically be accessed much faster than system memory.
shows the logical structure of the PPC405 cache arrays. Each cache array is
organized as a collection of
cachelines
. There are a total of 512 cachelines in a cache array,
divided evenly into two
ways
(one way contains 256 lines). Line
n
from way A and line
n
from way B make up a
set
of cachelines, also known as a
congruence class
. A cache array
contains a total of 256 sets, or congruence classes.
Each cacheline contains the following pieces of information:
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