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March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 11:
Instruction Set
R
This instruction is considered a “store” with respect to the above data-access exceptions. It
can cause data-access exceptions related to the EA even though the instruction is not
address specific (multiple addresses are selected by a single EA). This instruction does not
cause data address-compare (DAC) debug exceptions.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
Compatibility
This instruction is implementation specific and is not guaranteed to be supported by other
PowerPC processors.
Содержание Virtex-II Pro PPC405
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