Xilinx Virtex-II Pro PPC405, Руководство пользователя

Страница: 127 / 562

March 2002 Release www.xilinx.com 435
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Privileged Instructions
R
instruction. Epilog code is executed to unwind and deallocate the activation record, restore
pointers, and restore volatile registers. The interrupt handler executes a return-from-
interrupt instruction (
rfi ) to return to the application.
Table 4-4 lists the PowerPC system-linkage instructions. The sc instruction can be executed
from user mode and privileged mode. The rfi and rfci instructions are executed only from
privileged mode.
Processor-Control Instructions
In privileged mode, processor-control instructions are used to read from and write to the
machine-state register and the special-purpose registers. Instructions that access the time
base registers are also considered processor-control instructions, but are discussed
separately in
Chapter 8, Timer Resources .
Machine-State Register Instructions
The machine-state register instructions shown in Table 4-5 are used to read and write the
machine-state register (MSR) using a GPR as a destination or source register. The mtmsr
instruction shown in Table 4-5 is execution synchronizing. See Execution
Synchronization , page 342 , for more information.
Special-Purpose Register Instructions
The special-purpose register instructions shown in Table 4-6 are used to read and write the
special-purpose registers (SPRs) using a GPR as a destination or source register. The SPR
number (SPRN) shown in the operand syntax column can be specified as a decimal or
hexadecimal value in the assembler listing. Within the instruction opcode, this number is
Table 4-4: System-Linkage Instruction
Mnemonic Name Operation
Operand
Syntax
rfi Return from Interrupt
Return from noncritical-interrupt handler. See
Returning from Interrupt Handlers
, page 494
,
for more information.
—
rfci Return from Critical Interrupt
Return from critical-interrupt handler. See
Returning from Interrupt Handlers
, page 494
,
for more information.
—
sc System Call
Causes a system-call exception to occur. See
System-Call Interrupt (0x0C00)
, page 514
, for
more information.
—
Table 4-5: Machine-State Register Instructions
Mnemonic Name Operation
Operand
Syntax
mfmsr Move from Machine State Register r D is loaded with the contents of the machine-state
register.
r D
mtmsr Move to Machine State Register The machine-state register is loaded with the
contents of
r
S.
r S
wrtee
Write External Enable MSR[EE] (bit 16) is loaded with the value in
r
S
16
.
r
S
wrteei
Write External Enable Immediate MSR[EE] (bit 16) is loaded with the immediate
value of the instruction E field. E