Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 483
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Virtual-Mode Access Protection
R
Figure 6-8 shows the format of the ZPR register. The protection overrides encoded by the
zone fields are shown in Table 6-3 .
The ZPR is a privileged SPR with an address of 944 (0x3B0) and is read and written using
the
mfspr and mtspr instructions.
Effect of Access Protection on Cache-Control Instructions
The access-protection mechanisms apply to certain cache-control instructions, depending
on how those instructions affect data. Cache-control instructions—including those that
affect the instruction cache—are treated as data loads or data stores by the access-
protection mechanism. If an access-protection violation occurs, the resulting interrupt is a
data-storage interrupt. The following summarizes how access protection is applied to
cache-control instructions:
• Cache-control instructions that can modify data are treated as stores (writes) by the
access-protection mechanism. Instructions that can cause loss of data by invalidating
cachelines are also treated as stores. TLB write-protection and zone protection are
used to restrict access by these instructions as follows:
-
dcbi —Affected by TLBLO[WR] only. Because this is a privileged instruction,
access cannot be denied by zone protection.
- dcbz —Affected by TLBLO[WR] and (in user mode only) ZPR[Z n ]=00.
• Other cache-control instructions can invalidate an entire cache-congruence class.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 Z13 Z14 Z15
Figure 6-8: Zone-Protection Register (ZPR)
Table 6-3: Zone-Protection Register (ZPR) Bit Definitions
Bit Name Function Description
0:1 Z0 Zone 0 Protection User Mode (MSR[PR]
=
1)
00—Override V in TLB entry.
No access to the page is al-
lowed.
01—No override. Use V, WR,
and EX from TLB entry.
10—No override. Use V, WR,
and EX from TLB entry.
11—Override WR and EX.
Access the page as writable
and executable.
Privileged Mode (MSR[PR]
=
0)
00—No override. Use V, WR,
and EX from TLB entry.
01—No override. Use V, WR,
and EX from TLB entry.
10—Override WR and EX.
Access the page as writable
and executable.
11—Override WR and EX.
Access the page as writable
and executable.
2:3 Z1 Zone 1 Protection
4:5 Z2 Zone 2 Protection
6:7 Z3 Zone 3 Protection
8:9 Z4 Zone 4 Protection
10:11 Z5 Zone 5 Protection
12:13 Z6 Zone 6 Protection
14:15 Z7 Zone 7 Protection
16:17 Z8 Zone 8 Protection
18:19 Z9 Zone 9 Protection
20:21 Z10 Zone 10 Protection
22:23 Z11 Zone 11 Protection
24:25 Z12 Zone 12 Protection
26:27 Z13 Zone 13 Protection
28:29 Z14 Zone 14 Protection
30:31 Z15 Zone 15 Protection