Xilinx Virtex-II Pro PPC405, Руководство пользователя

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382 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
Load Word and Zero
Table 3-16 lists the PowerPC load word and zero instructions. These instructions load a word
from memory into r D.
Load Halfword Algebraic
Table 3-17 lists the PowerPC load halfword algebraic instructions. These instructions load a
halfword from memory into the lower-16 bits of r D. The upper-16 bits of r D are filled with
a copy of the most-significant bit (bit 16) of the operand.
Table 3-15: Load Halfword and Zero Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
lhz Load Halfword and Zero Register-indirect with immediate index
EA
=
( r A|0)
+
d
r D,d( r A)
lhzu Load Halfword and Zero with Update Register-indirect with immediate index
EA
=
( r A)
+
d
r A
←
EA
r A
≠
0, r A
≠
r D
lhzx Load Halfword and Zero Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r D, r A, r B
lhzux Load Halfword and Zero with Update
Indexed Register-indirect with index
EA
=
( r A)
+
( r B)
r A
←
EA
r A
≠
0, r A
≠
r D
Table 3-16:
Load-Word and Zero Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
lwz Load Word and Zero Register-indirect with immediate index
EA
=
( r A|0)
+
d
r D,d( r A)
lwzu Load Word and Zero with Update Register-indirect with immediate index
EA
=
( r A)
+
d
r A
←
EA
r A
≠
0, r A
≠
r D
lwzx Load Word and Zero Indexed Register-indirect with index
EA
=
( r A|0)
+
( r B)
r D, r A, r B
lwzux Load Word and Zero with Update
Indexed Register-indirect with index
EA
=
( r A)
+
( r B)
r A
←
EA
r A
≠
0, r A
≠
r D