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173
Index Registers
Section 4-15
tions shown in the following table. Use these instructions to operate on the
Index Registers as pointers.
The Index Registers cannot be directly addressed in any other instructions,
although they can usually be used for indirect addressing.
The SRCH(181), MAX(182), and MIN(183) instructions can output the PLC
memory address of the word with the desired value (search value, maximum,
or minimum) to IR0. In this case, IR0 can be used in later instructions to
access the contents of that word.
4-15-1 Using Index Registers
Processing of multiple (identical) instructions such as consecutive addresses
for table data can be merged into one instruction by combining repetitive pro-
cessing (e.g., FOR(513) and NEXT(514)instructions) with indirect addressing
using Index Registers, thereby simplifying programming.
The Index operation uses the following procedure.
1.
PLC memory addresses for the addresses in the Index Registers are
stored using a MOVR instruction.
2.
Operation is then executed by indirectly addressing Index Registers to the
operand for Instruction A.
3.
The addresses are moved using processing such as adding, subtracting,
incrementing, or decrementing the Index Register (see note).
Instruction group
Instruction name
Mnemonic
Data Movement
Instructions
MOVE TO REGISTER
MOVR(560)
MOVE TIMER/COUNTER PV TO REG-
ISTER
MOVRW(561)
DOUBLE MOVE
MOVL(498)
DOUBLE DATA EXCHANGE
XCGL(562)
Table Data Processing
Instructions
SET RECORD LOCATION
SETR(635)
GET RECORD NUMBER
GETR(636)
Increment/Decrement
Instructions
DOUBLE INCREMENT BINARY
++L(591)
DOUBLE DECREMENT BINARY
– –L(593)
Comparison Instructions
DOUBLE EQUAL
=L(301)
DOUBLE NOT EQUAL
< >
L(306)
DOUBLE LESS THAN
<
L(311)
DOUBLE LESS THAN OR EQUAL
<
=L(316)
DOUBLE GREATER THAN
>
L(321)
DOUBLE GREATER THAN OR EQUAL
>
=L(326)
DOUBLE COMPARE
CMPL(060)
Symbol Math Instructions DOUBLE SIGNED BINARY ADD WITH-
OUT CARRY
+L(401)
DOUBLE SIGNED BINARY SUBTRACT
WITHOUT CARRY
–L(411)
IR0
,IR0
Instruction execution
repeatedly incrementing
IR0 by 1
Instruction
Indirect
addressing
Table data
Summary of Contents for CP1H CPU UNITS - PROGRAMMING 05-2007
Page 2: ......
Page 3: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised March 2009...
Page 4: ...iv...
Page 10: ...x...
Page 18: ...xviii...
Page 22: ...xxii...
Page 34: ...xxxiv Conformance to EC Directives 6...
Page 174: ...140 CP series Expansion I O Unit Wiring Section 3 6...
Page 370: ...336 Analog I O XA CPU Units Section 5 5...
Page 552: ...518 Trouble Shooting Section 8 7...
Page 595: ...561 Sample Application Section 9 12 Network Settings Network Tab Network Settings Driver Tab...
Page 598: ...564 Sample Application Section 9 12...
Page 642: ...608 Standard Models Appendix A...
Page 652: ...618 Dimensions Diagrams Appendix B...
Page 745: ...711 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 746: ...712 Connections to Serial Communications Option Boards Appendix F...
Page 776: ...742 PLC Setup Appendix G...
Page 778: ...744 Specifications for External Power Supply Expansion Appendix H...
Page 786: ...752 Revision History...