194
Interrupt Functions
Section 5-1
Procedure
Note
The input interrupt (counter mode) function is one of the input interrupt func-
tions and executes an interrupt based on the pulse count. If the input pulse
frequency is too high, interrupts will occur too frequently and prevent normal
cyclic task processing. In this case, cycle time too long errors may occur or
the pulse input may not be read.
The maximum total frequency of the counter-mode interrupt inputs is 5 kHz.
Even in this case, the high frequencies may adversely affect other devices’
operation or the system load, so check the system’s operation thoroughly
before using the counters at high frequencies.
PLC Setup
The procedures for using the CX-Programmer to set the PLC Setup are the
same as the procedures for input interrupts (direct mode). Refer to
5-1-2 Input
Interrupts (Direct Mode)
for details.
Writing the Ladder
Program
MSKS(690) Settings
The MSKS(690) instruction must be executed in order to use input interrupts.
The settings made with MSKS(690) are enabled with just one execution, so in
general execute MSKS(690) in just one cycle using an up-differentiated condi-
tion.
MSKS(690) has the following two functions and three of the instructions are
used in combination. If up-differentiated input pulses are being used, the first
MSKS(690) instruction can be omitted since the input is set for up-differentia-
tion by default.
Select the input interrupts (counter
mode).
• Determine the inputs to be used for input
interrupts and corresponding task numbers.
↓
Wire the inputs.
• Wire the inputs.
↓
Set the PLC Setup.
• Use the CX-Programmer to select the inter-
rupt inputs in the PLC Setup.
↓
Set the counter SVs.
• Set the interrupt counter SVs in the corre-
sponding AR Area words.
↓
Write the ladder program.
• Write the programs for the corresponding
interrupt task numbers.
• Use MSKS(690) to specify up-differentiation
or down-differentiation.
• Use MSKS(690) to enable input interrupts (in
counter mode).
@MSKS(690)
N
S
@MSKS(690)
N
S
Execution condition
2. Enables or disables the input interrupt.
1. Specifies up-differentiated or
down-differentiated inputs.
Summary of Contents for CP1H CPU UNITS - PROGRAMMING 05-2007
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Page 3: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised March 2009...
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Page 22: ...xxii...
Page 34: ...xxxiv Conformance to EC Directives 6...
Page 174: ...140 CP series Expansion I O Unit Wiring Section 3 6...
Page 370: ...336 Analog I O XA CPU Units Section 5 5...
Page 552: ...518 Trouble Shooting Section 8 7...
Page 595: ...561 Sample Application Section 9 12 Network Settings Network Tab Network Settings Driver Tab...
Page 598: ...564 Sample Application Section 9 12...
Page 642: ...608 Standard Models Appendix A...
Page 652: ...618 Dimensions Diagrams Appendix B...
Page 745: ...711 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 746: ...712 Connections to Serial Communications Option Boards Appendix F...
Page 776: ...742 PLC Setup Appendix G...
Page 778: ...744 Specifications for External Power Supply Expansion Appendix H...
Page 786: ...752 Revision History...