Omron CP1H CPU UNITS - PROGRAMMING 05-2007, Operation Manual

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Interrupt Functions
Section 5-1
If you click the X Button in the upper-right corner of the window, you can cre-
ate the program that will be executed as interrupt task 140.
The programs allocated to each task are independent and an END(001)
instruction must be input at the end of each program.
Interrupt Task Priority
The input interrupts (direct mode and counter mode), high-speed counter
interrupts, scheduled interrupts, and external interrupts all have the same pri-
ority. If interrupt task A (an input interrupt, for example) is being executed
when interrupt task B (a scheduled interrupt, for example) is called, task A
processing will not be interrupted. Task B processing will be started when task
A is completed.
If two different types of interrupt occur simultaneously, they are executed in
the following order:
If two of the same type interrupt occur simultaneously, the task with the lower
interrupt task number is executed first.
Note If a user program is likely to generate multiple interrupts simultaneously, the
interrupt tasks will be executed in the order shown above, so it may take some
time from the occurrence of the interrupt condition to the actual execution of
the corresponding interrupt task. In particular, it is possible that scheduled
interrupts will not be executed in the preset time, so the program must be
designed to avoid interrupt conflicts if necessary.
Duplicate Processing
in Cyclic and Interrupt
Tasks
If a memory address is processed both by a cyclic task and an interrupt task,
an interrupt mask must be set to disable interrupts.
When an interrupt occurs, execution of the cyclic task will be interrupted
immediately, even during execution of a cyclic task’s instruction, and the par-
tially processed data is saved. After the interrupt task is completed, process-
ing returns to the cyclic task and the interrupted processing restarts with the
data saved before the interrupt processing. If the interrupt task overwrites a
memory address used by one of the interrupted instruction’s operands, that
overwrite may not be reflected after the saved data is restored as processing
returns to the cyclic task.
To prevent an instruction from being interrupted during processing, enter
DI(693) just before the instruction to disable interrupts and EI(694) just after
the instruction to enable interrupts again.
External
interrupt
>
Input interrupt
(direct mode or
counter mode)
>
High-speed
counter inter-
rupt
>
Scheduled
interrupt