User Manual
527
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
Capture/Compare Unit 6 (CCU6)
18.3.4
Compare Mode Output Path
gives an overview on the signal path from a channel State Bit to its output pin in its simplest form.
As illustrated, a user has a variety of controls to determine the desired output signal switching behavior in
relation to the current state of the State Bit, CC6xST. Please refer to
for details on the output
modulation.
Figure 133 Compare Mode Simplified Output Path Diagram
The output path is based on signals that are defined as active or passive. The terms active and passive are not
related to output levels, but to internal actions. This mainly applies for the modulation, where T12 and T13
signals are combined with the multi-channel signals and the trap function. The Output level Selection allows
the user to define the output level at the output pin for the passive state (inverted level for the active state). It
is recommended to configure this block in a way that an external power switch is switched off while the CCU6
delivers an output signal in the passive state.
18.3.4.1 Dead-Time Generation
The generation of (complementary) signals for the High Side and the low-side switches of one power inverter
phase is based on the same compare channel. For example, if the High Side switch should be active while the
T12 counter value is above the compare value (State Bit = 1), then the low-side switch should be active while
the counter value is below the compare value (State Bit = 0).
In most cases, the switching behavior of the connected power switches is not symmetrical concerning the
switch-on and switch-off times. A general problem arises if the time for switch-on is smaller than the time for
switch-off of the power device. In this case, a short-circuit can occur in the inverter bridge leg, which may
damage the complete system. In order to solve this problem by HW, this capture/compare unit contains a
programmable Dead-Time Generation Block, that delays the passive to active edge of the switching signals by
a programmable time (the active to passive edge is not delayed).
The Dead-Time Generation Block, illustrated in
, is built in a similar way for all three channels of
T12. It is controlled by bits in register T12DTC. Any change of a CC6xST State Bit activates the corresponding
Dead-Time Counter, that is clocked with the same input clock as T12 (
f
T12
). The length of the dead-time can be
programmed by bit field DTM. This value is identical for all three channels. Writing TCTR4.DTRES = 1 sets all
dead-times to passive.
CCU6_MCA05519
Level
Select
Level
Select
CC6x
COUT6x
COUT6x_O
CC6x_O
Dead-Time
Counters
T12
State Selection
CC6xST
CC6xST
CC6xPS
COUT6xPS
T12 Output
Modulation
PSLy
PSLy+1
Output Level
Selection
CC61ST
Dead-Time
Generation
T12
State Bits
CC60ST
CC62ST